Hello Sylvain, I have tested the draft branch and find that it now t

0.7 seconds delay after reset on the icestick. about silice HOT 2 CLOSED

at91rm9200 commented on June 11, 2024

0.7 seconds delay after reset on the icestick.

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Comments (2)

sylefeb commented on June 11, 2024

Hello Bernd,

Indeed, this is due to this part of the framework (the RST counter):

Silice/frameworks/boards/icestick/icestick.v

Lines 156 to 178 in 7540cae

 reg ready = 0; 

 reg [23:0] RST_d; 

 reg [23:0] RST_q; 

 always @* begin 

 RST_d = RST_q[23] ? RST_q : RST_q + 1; 

 end 

 always @(posedge CLK) begin 

 if (ready) begin 

 RST_q <= RST_d; 

 end else begin 

 ready <= 1; 

 RST_q <= 0; 

 end 

 end 

 wire run_main; 

 assign run_main = 1'b1; 

 M_main __main( 

 .clock(CLK), 

 .reset(~RST_q[23]),

One issue on the ice40 is that BRAMs take time to initialize and as I encountered some problems I increased the delay very significantly, likely way too much! I'll refine this to make it as short as possible.

(If you need a quick workaround you can simply replace icestick.v by the one from the master branch, but I'll to look into this soon).

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at91rm9200 commented on June 11, 2024

Hello Sylvain,

thank you for the explanation. I replaced icestick.v and everything is fine now.

Regards, Bernd.

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0.7 seconds delay after reset on the icestick. about silice HOT 2 CLOSED

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	reg ready = 0;
	reg [23:0] RST_d;
	reg [23:0] RST_q;

	always @* begin
	RST_d = RST_q[23] ? RST_q : RST_q + 1;
	end

	always @(posedge CLK) begin
	if (ready) begin
	RST_q <= RST_d;
	end else begin
	ready <= 1;
	RST_q <= 0;
	end
	end

	wire run_main;
	assign run_main = 1'b1;

	M_main __main(
	.clock(CLK),
	.reset(~RST_q[23]),