This file is the introduction on what this project is and how to contribute.
The actual contents are here.

Beginners usually find themselves hard to understand the difference between RTL design and behavioral (or program) design. Though there are online cheatsheets about the grammar of verilog, they neither explicitly mark the synthesizable part, nor introduce the structure of digital circuits.
So, we may write this document as a guide for beginners to know "how the structure of their design looks like".

Just submit issues or PRs. Please mark your commits as:

• [Add] add new samples that might help.
• [Detail] give further description of an existing circuit.
• [Fix] fix bugs of current document.