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The behavior of the EX register when performing a DIV is incorrect. EX should be set to ((b<<16)/a) & 0xffff as per the spec, rather than (b/a) << 16 & 0xffff, which will always be zero in 16 bit division.

Code

jmp start
    :data1      dat 0,0,0,0
    :data2      dat 0,0,0,0
    :data3      dat 0x0000
:start
    mov data1, sp   ; saving initial stack pointer if we should inline into other program (OS)
    SET [0x6], 0x3000
    SET I, [0x6]

    SET [data2], 0x4000
    SET I, [data2]

Compiles into

PC   SP   OV   A    B    C    X    Y    Z    I    J    Instruction
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- -----------
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 JMP 0x000b
000b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MOV 0x000a, SP
000d 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MOV [0x0006], 0x3000
0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MOV I, [0x0006]
0012 0000 0000 0000 0000 0000 0000 0000 0000 3000 0000 MOV [0x0006], 0x4000
0015 0000 0000 0000 0000 0000 0000 0000 0000 3000 0000 MOV I, [0x4000]
0017 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MOV PUSH, 3

However 0015 should be MOV I, [0x0006] too.

Do you have some macro support in your plan?
However it could be done with external preprocessor. For example I tried m4: https://github.com/rayslava/dcpu16_tools

In your VM, you initialize 65536 words of RAM, whereas the specification calls for 0x10000 words of ram (128kw).
Is there something I'm missing?

They say, Notch released new instruction set…

https://github.com/0x10cStandardsCommittee/0x10c-Standards/blob/master/ASM/Draft_DCPU-16_Specification_v2.txt

Just something like DATA keyword for values longer than WORD can do.

:string
    data 0,1,2,3,4,5,6,7
    data 'H','e','l','l','o'

And maybe some strings support?
judofyr's rcpu for example orients onto 0x8000 for string output and 0x9000 for input.

I'm getting:

hello.asm:10: invalid operand
hello.asm:10: >> :nextchar ife [data+i], 0 ; If the character is 0 ..
<<

When I try running Notch's "hello world" code through a16.

https://raw.github.com/jtauber/DCPU-16-Examples/master/hello.asm

Any thoughts on that? I haven't completely traced through your code to see where things go awry, yet.

If I do

Last lines are:

< ILLEGAL OPCODE >

If it's an example, should be OK, isn't it?

I couldn't definitely understand from reference manual if it should work that way but assembler should at least exit with error or warn user but not to compile wrong code silently.

For example:

SET [0x30], A
SET [0x30], [A]
SET A, 0x30
SET [A], 0x30

Compiles into

SET [0x0030], A
SET [0x0030], A
SET A, 0x0030
SET A, 0x0030

I think there is a problem somewhere in bracket parsing algorithm.