A 16-bit multi-cycle CPU described in VHDL and to be implemented on an FPGA.
This project is part of the course Digital Systems (EE224), at IIT Bombay (2023)
alu.vhdl
: Capable of performing ADD, SUB, MUL, AND, ORA and IMP and uses registers(C,Z flags)
Mux1_2_1.vhdl
: 2-to-1 MUXMux1_4_1.vhdl
: 4-to-1 MUXMux1_8_1.vhdl
: 8-to-1 MUX
Mux1_8_1.vhdl
: 8-to-1 MUX
Register16BIT.vhdl
: 16-bit register with synchronous write and asynchonous readRegister_file.vhdl
: Set of 8 16-bit registers
Memory.vhdl
: Array of 512 8-bit vectors
DUT_ALU.vhdl
: Top-Level entity for ALU.vhdl
DUT_Reg16BIT.vhdl
: Top-Level entity for Reg16BIT.vhdl
CPU.vhdl
: Main code