This repository contains the gateware for the Phaser 4 channel 1 GS/s DAC arbitrary waveform generator.

Funded by Oxford, Oregon, MITLL, QUARTIQ.

The hardware design repository is over at Sinara.

NBViewer link

• half-hand-filter: ideas and sketches for a 1/10 (samples per clock cycle) to 2/1 interpolator cascade, analysis of other interpolator approaches, comparison of CIC/HBF/FIR, CIC droop compensation filter
• cic: ideas for CIC implementations and tests of interpolation modes

With vivado and a vivado-compatible JTAG dongle, to load (volatile) a bitstream onto the FPGA, use:

vivado -mode batch -source load.tcl -tclargs build/phaser.bit

To flash it, use:

vivado -mode batch -source flash.tcl -tclargs build/phaser.bit

With openocd and a JTAG dongle that fits the connector and has openocd support it should also be possible to load and flash using the xc7a support and the jtagspi proxy bitstreams.