The goal of this project is be able to take any application and produce a RISC-V CPU implementation best suited for it, Removing hardware from a traditional RISC-V CPU that wouldn't be used by the application.

Here goes the code responsible for analyzing compiled .s files and generating its corresponding verilog code.

RISC-V implementation in verilog capable of running all RISC-V instructions

Here goes the application we are optimizing for and its associated .s file.

This is a JSON file that has a list of all RISC-V instructions and their extensions to more easily query and identify them in code.

Install RISC-V compiler

# Debian
$ sudo apt install g++-riscv64-linux-gnu

# Arch
$ sudo pacman -S riscv64-linux-gnu-gcc

Compile C++/C code into .s assembly instruction file

# don't fprget to cd to ./src/risccv code

# Debian
$ g++-riscv64-linux-gnu -S <C++/C file>

# Arch
$ riscv64-linux-gnu-g++ -S <C++/C file>

Now you can inspect which instructions exactly this program uses.

Run python code under /analysis and it will create a bar chart of the instructions used in the .s file under /riscv code.

Download icarus verilog

# Debian
$ sudo apt install iverilog

# Arch
$ sudo pacman -S iverilog

Compile verilog code using list of all .v files as found under icarus_ref.txt. (make sure file names are in order of encapsulation/dependency. this is why we cannot use *.v to compile)

# don't forget to cd to ./src/riscv CPU
$ iverilog -o ricv -c icarus_ref.txt

Run implementation. text output of asserts should pop up in terminal.

$ vvp riscv

Produce verilog files according to application requirement

Install GTKwave

$ sudo apt install gtkwave

Make sure you add this to the beginning of you simulation's initial begin. Just replace "riscv" with the simulation modules name

$dumpfile("riscv.vcd");
$dumpvars(0, rsicv);

View waveform.

$ sudo gtkwave "<directory of .vcd file>"

• Finish implementation of RISC-V verilog implementation able of running all RISC-V instructions.
• Categorize what part of the RISC-V CPU each instruction uses.
• Make program that creates verilog code that implements RISC-V CPU with the minimum hardware required for an application.

• Replace instructions rarely used by application by slower instructions but use less hardware.
• Custom compiler that is able to produce RISC-V code while avoiding specific instructions.
• Create a sort of "speed", "power" and "cost" profiles that alters which instructions are implemented and how they are implemented to better suit an end case.