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DECA Altera Max 10 FPGA Labs
Hi @ all,
I tried to compile the last example 8_MIPI_to_HDMI_Terasic with Quartus 15.1.0.
Without upgrading the IPs I got only the green background screen from the Mixer. When I upgraded the IPs the following error occurs during "Analysis & Synthesis":
Error (12002): Port "rx_outclock" does not exist in macrofunction "mipi_lvds_inst"
The file mipi_cs2_stream.v (where the error is located in) is encrypted, so I can't look deeper to find the issue. Maybe only the name of the port is changed during IP upgrade.
The issue is the same in the completed lab and after completing the workshop_lab according to the manual. I triple checked the names in the Qsys-tool, but can't find any mistakes or differences compered to mipi_vip.qsys or mipi_vip - final.qsys out of the completed lab.
I used the last version 1.2.2, directly downloaded as zip from github.
Can you please provide some help to fix the issue?
Thank You,
Robert
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