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aes-128

RTL implementation of the AES algorithm with 128-bit key using Verilog.

analog-mixed-signal-simulation-and-modeling

This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.

ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

elevator-controller

VHDL RTL Design, Verification, and FPGA Implementation of an Elevator Controller

gray-code-counter

This project involved designing a digital circuit for a gray code representation on a seven-segment display, then using Quartus Prime and Altera’s FPGA to implement the counter.

matlab-study-notes

modeling-of-90nm-nmos-and-pmos-fets

Analytical model is developed using Matlab describing the transistor operation for both an N- and P-type MOSFETs.

qpsk-communication-system-modeling

A MATLAB implementation for quadrature phase-shift keying communication system.

semiconductorscalculator

Using MATLAB GUI, this project is a calculators for some important semiconductors' parameters as the number of electrons, holes and the fermi level for some materials depending on the temperature and doping.

snakegame

This project is done using C++, SFML library, and OOP concepts.

vhdl-exercises

My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.

washing-machine-controller

Verilog HDL implementation and verification of a controller unit of washing machine.