This repository holds assignments done as a part of the course EE2003, Computer Organisation, Jul - Nov 2021 Semester. Each sub-folder has the problem statement in detail, breif description of each of the sub-folders is as follows:

• a1: Implements a sequential multiplier in Verilog.
• a2: Implements fibonacci number generation in RISC-V assembly.
• a3: Implements a RISC-V soft-core with ALU and Branch instructions.
• a4: Implements a RISC-V soft-core with all instructions expect system instructions.
• a4_synthesis: Synthesis of RISC-V soft-core from a4 using Yosys.
• a5: Interfacing of sequential multiplier with picoRV32 core.