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本次实验所涉及的模型机使用了一种采取精简指令集的架构,仿照MIPS16 设计 并进行简化。本实验使用的指令集架构包含8 个通用寄存器,数据总线和地址总线宽 度均为16 位。支持乘法运算,实现了无符号数原码阵列乘法器。实现了常用基本功能, 包括加减乘和逻辑运算、寄存器置数、多种寻址方式的RAM 读写、无条件跳转、有条 件跳转、栈、子程序等。采用16 位固定字长指令简化实现。

Verilog 39.56% Coq 0.04% HTML 43.89% SystemVerilog 0.90% Mathematica 0.13% Scheme 0.10% VHDL 13.80% Stata 0.12% Standard ML 0.01% C++ 1.45%

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