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Linux on Litex for BlackParrot Core

Makefile 100.00%

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troibe chipyard mik1234mc t-platz

linux-on-litex-blackparrot's Issues

Fix slow boot

After switching from 64bit CSRs to 32bit CSRs the boot process takes about 30m instead of 10m.
Try finding out why that's the case.
This applies particularly to the Press Q or ESC to abort boot completely. part which then leads to a timeout in case of inaction.

Linux boot hangs in litex_sim.

Hello! I'm trying to reproduce Linux boot using litex_sim, but seems like boot process hangs at the certain point:
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 [ 0.000000] Linux version 4.15.0-00049-g0893cdb507ad (martin@martin-ThinkPad-T14-Gen-1) (gcc version 7.2.0 (GCC)) #1 SMP Tue Jul 27 02:49:52 CEST 2021 [ 0.000000] bootconsole [early0] enabled [ 0.000000] Initial ramdisk at: 0x (ptrval) (5214208 bytes) [ 0.000000] Zone ranges: [ 0.000000] DMA32 [mem 0x0000000080200000-0x0000000083ffffff] [ 0.000000] Normal [mem 0x0000000084000000-0x0000083fffffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000080200000-0x0000000083ffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x0000000083ffffff] [ 0.000000] Cannot allocate SWIOTLB buffer [ 0.000000] elf_hwcap is 0x1129 [ 0.000000] percpu: Embedded 14 pages/cpu @ (ptrval) s28632 r0 d28712 u57344 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 15655 [ 0.000000] Kernel command line: [ 0.000000] Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Sorting __ex_table... [ 0.000000] Memory: 50976K/63488K available (4310K kernel code, 219K rwdata, 841K rodata, 5287K init, 780K bss, 12512K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU event tracing is enabled. [ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 [ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 28210892935680 ns [ 0.007128] sched_clock: 64 bits at 125kHz, resolution 8000ns, wraps every 17592186044000ns [ 0.130504] console [hvc0] enabled [ 0.130504] console [hvc0] enabled [ 0.183352] bootconsole [early0] disabled [ 0.183352] bootconsole [early0] disabled [ 0.292048] Calibrating delay loop (skipped), value calculated using timer frequency.. 0.25 BogoMIPS (lpj=1250) [ 0.373240] pid_max: default: 32768 minimum: 301 [ 0.820656] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.909464] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 5.959248] Hierarchical SRCU implementation. [ 8.297072] smp: Bringing up secondary CPUs ... [ 8.363144] smp: Brought up 1 node, 1 CPU [ 10.613224] devtmpfs: initialized [ 14.547200] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 14.671200] futex hash table entries: 256 (order: 2, 16384 bytes) [ 16.885384] random: get_random_u32 called from bucket_table_alloc+0x134/0x3c0 with crng_init=0 [ 17.704808] NET: Registered protocol family 16 [ 40.927928] vgaarb: loaded [ 42.148584] SCSI subsystem initialized [ 44.191576] usbcore: registered new interface driver usbfs [ 44.436904] usbcore: registered new interface driver hub [ 44.709496] usbcore: registered new device driver usb [ 45.195544] pps_core: LinuxPPS API ver. 1 registered [ 45.251392] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]> [ 45.395344] PTP clock support registered
The output then freezes and nothing happens for days. Am I doing something wrong?

Add missing external files

Currently the CI fails with:

%Error: Cannot find file containing module: /home/runner/work/linux-on-litex-blackparrot/linux-on-litex-blackparrot/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v

Extend timeout for CI

Having issues in reproducing the work

First, we thank you for your impressive work. We would like to reproduce your work on our Artix A7 board.
However, we are not able to do reproduce it as we are getting the below error. Can you please help us in resolving this issue?

This is with the master branch of litex.

ERROR: [Synth 8-1766] cannot open include file bsg_defines.v [/noback/xqn/LinuxBlackParrot/linux-on-litex-blackparrot.new/pythondata-cpu-blackparrot/pythondata_
cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v:7]
INFO: [Synth 8-2350] module bsg_cache_pkg ignored due to previous errors [/noback/xqn/LinuxBlackParrot/linux-on-litex-blackparrot.new/pythondata-cpu-blackparrot
/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v:137]
Failed to read verilog '/noback/xqn/LinuxBlackParrot/linux-on-litex-blackparrot.new/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/black-p
arrot/external/basejump_stl/bsg_cache/bsg_cache_pkg.v'
INFO: [Common 17-83] Releasing license: Synthesis
7 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Sun Aug 21 23:14:58 2022...
Traceback (most recent call last):
      File "litex-boards/litex_boards/targets/digilent_arty.py", line 215, in <module>
          main()
        File "litex-boards/litex_boards/targets/digilent_arty.py", line 204, in main
          builder.build(**builder_kwargs)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/soc/integration/builder.py", line 357, in build
          vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/soc/integration/soc.py", line 1277, in build
          return self.platform.build(self, *args, **kwargs)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/build/xilinx/platform.py", line 73, in build
          return self.toolchain.build(self, *args, **kwargs)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/build/xilinx/vivado.py", line 130, in build
          return GenericToolchain.build(self, platform, fragment, **kwargs)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/build/generic_toolchain.py", line 113, in build
          self.run_script(script)
        File "/home/xqn/LinuxBlackParrot/linux-on-litex-blackparrot/litex/litex/build/xilinx/vivado.py", line 373, in run_script
          raise OSError("Error occured during Vivado's script execution.: "+script)
      OSError: Error occured during Vivado's script execution.: build_digilent_arty.sh

If I use the litex submodule of this repository, I am facing the below error.

Traceback (most recent call last):
  File "litex-boards/litex_boards/targets/digilent_arty.py", line 215, in <module>
    main()
  File "litex-boards/litex_boards/targets/digilent_arty.py", line 151, in main
    from litex.soc.integration.soc import LiteXSoCArgumentParser
ImportError: cannot import name 'LiteXSoCArgumentParser' from 'litex.soc.integration.soc' (/noback/nqx/GoogleCFU/LinuxBlackParrot/linux-on-litex-blackparrot.new/litex/litex/soc/integration/soc.py)

Simulation error

Hi , I am following your Readme.md and during simulation i am inputting in terminal : make simulation command and gettiing :
litex_sim --cpu-type blackparrot
--cpu-variant standard
--with-sdram
--sdram-init prebuilt/simulation/boot_simulation.bin
Traceback (most recent call last):
File "/home/.local/bin/litex_sim", line 33, in
sys.exit(load_entry_point('litex', 'console_scripts', 'litex_sim')())
File "/home/.local/bin/litex_sim", line 25, in importlib_load_entry_point
return next(matches).load()
File "/home//anaconda3/lib/python3.10/importlib/metadata/init.py", line 171, in load
module = import_module(match.group('module'))
File "/home/anaconda3/lib/python3.10/importlib/init.py", line 126, in import_module
return _bootstrap._gcd_import(name[level:], package, level)
File "", line 1050, in _gcd_import
File "", line 1027, in _find_and_load
File "", line 1006, in _find_and_load_unlocked
File "", line 688, in _load_unlocked
File "", line 883, in exec_module
File "", line 241, in _call_with_frames_removed
File "/home /Desktop/bpp/linux-on-litex-blackparrot/litex/litex/tools/litex_sim.py", line 31, in
from litedram.phy.model import sdram_module_nphases, get_sdram_phy_settings
File "/home/Desktop/bpp/linux-on-litex-blackparrot/litedram/litedram/phy/init.py", line 5, in
from litedram.phy.usddrphy import USDDRPHY, USPDDRPHY
File "/home/Desktop/bpp/linux-on-litex-blackparrot/litedram/litedram/phy/usddrphy.py", line 18, in
from litex.gen.genlib.misc import WaitTimer
ModuleNotFoundError: No module named 'litex.gen.genlib'
make: *** [Makefile:30: simulation] Error 1
Is there Any error related to installation of litex ? thanks in advance

Use bootrom properly

Currently we need to modify litex_sim to set the ROM_BOOT_ADDRESS to 0x8000000 as this is the address that Blackparrot jumps to by default.
With proper bootrom support we should be able to modify this default jump address to 0x10000000 which is where Litex expects the execution to continue. We therefore afterwards should be able use the default litex_sim script.

Prerequisite
With black-parrot/black-parrot#547 proper bootrom support was introduced.
Therefore this requires updating blackparrot.

This is the output that I'm getting currently:

%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_arbitrate.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_branch.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_dir_segment.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_inst_predecode.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_inst_ram.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_inst_stall.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_pending_bits.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_spec_bits.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_src_sel.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_me/src/v/cce/bp_cce_wrapper.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_nd_socket.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cacc_vdp.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cacc_tile.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cacc_tile_node.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cacc_complex.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_sacc_vdp.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_sacc_tile.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_sacc_tile_node.v
%Error: Cannot find file containing module: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_sacc_complex.v
%Error: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cfg.v:38:5: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER
   38 |     bp_cce_mem_req_size_e                        size;          
      |     ^~~~~~~~~~~~~~~~~~~~~
%Error: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cfg.v:38:3: syntax error, unexpected '}'
   38 |   } bp_cce_mem_msg_header_s;                                    
      |   ^
%Error: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cfg.v:38:5: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER
   38 |     bp_cce_mem_msg_header_s                      header;        
      |     ^~~~~~~~~~~~~~~~~~~~~~~
%Error: Internal Error: /home/martin/coding/litex/pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog/bp_top/src/v/bp_cfg.v:2:8: ../V3ParseSym.h:119: Symbols suggest ending STRUCTDTYPE but parser thinks ending MODULE 'bp_cfg'
    2 | module bp_cfg
      |        ^~~~~~

scanakci / linux-on-litex-blackparrot Goto Github PK

linux-on-litex-blackparrot's People

Contributors

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Watchers

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linux-on-litex-blackparrot's Issues

Fix slow boot

Linux boot hangs in litex_sim.

Add missing external files

Extend timeout for CI

Having issues in reproducing the work

Simulation error

Use bootrom properly

Remove stale branches

Simplify README

Missing files and errors on simulation start

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