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msp430's Introduction

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msp430

Low level access to MSP430 microcontrollers

This crate is based on cortex-m crate by Jorge Aparicio (@japaric).

This crate requires a nightly rust due to the use of the new asm! (0.3.0 and above), llvm_asm! (0.2.2) or old asm! (0.2.1 and below) macros. The below table contains compilers which are known to work:

msp430 version rustc compiler
0.3.0 nightly-2022-01-24
0.2.2 nightly-2020-04-22
0.2.1 nightly-2020-01-04

Features

The critical-section-single-core feature provides a critical section implementation based upon disabling interrupts.

Critical sections by disabling interrupts are a valuable way to access I/O and shared data safely in msp430. However, rustc/LLVM does not always optimize critical sections well in terms of space. For example, sometimes rustc/LLVM will create two copies of interrupt enable assembly code when exiting a critical section that contains a branch- one copy each for branch-taken/branch-not-taken.

This crate provides three features for giving hints to rustc/LLVM for how to optimize critical sections for size. Both critical_section::with and the interrupt::free critical sections are supported, with and without the critical-section feature above:

  • outline-cs-acq: Hint to rustc/LLVM that each critical section entry should be a call to a single copy of an acquire function (disable interrupts).
  • outline-cs-rel: Hint to rustc/LLVM that each critical section exit should be a call to a single copy of a release function (enable interrupts if not in a nested critical section).
  • outline-cs: Convenience feature for enabling both of the above at the same time.

If saving space is a concern in your application, you should experiment with which features provide the best size savings and balance this against the execution overhead of the extra function calls due to outlining. The execution overhead of enabling each hint is ~5 + 2 clock cycles for each critical section- at least a CALL and RET instruction.

License

Licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

msp430's People

Contributors

adamgreig avatar bors[bot] avatar cr1901 avatar homunkulus avatar japaric avatar pftbest avatar sbourdeauducq avatar schodet avatar taiki-e avatar thejpster avatar therealprof avatar vadzimdambrouski avatar whitequark avatar yuhanliin avatar

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msp430's Issues

Interrupt enable/disable should be using `compiler_fence`.

For example, in cortex_m:

pub fn disable() {
    unsafe {
        asm!("cpsid i", options(nomem, nostack, preserves_flags));
    }

    // Ensure no subsequent memory accesses are reordered to before interrupts are disabled.
    compiler_fence(Ordering::SeqCst);
}

compiler_fence does not currently work properly for the msp430 backend. Thank you @eddyb for pointing this out to me.

barrier and nop are also likely affected; barrier needs a fence to prevent reordering, and both functions assume that Rust will not optimize out inline ASM (which I'm not sure is true).

Bump `bare-metal` to 1.0.0

This introduces the Cloneable CriticalSection to MSP430. We need to make sure that it's not possible to clone the starting CriticalSections provided by msp430-rt into static variables, since that might be unsound. This means that the starting CriticalSections shouldn't have 'static lifetimes.

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