rj45 / digilogic Goto Github PK

A way to import or sync or diff a KiCAD netlist with the circuit to have some assurance the circuits have the same wiring

subcircuits written in verilog could be simulated in iverilog. Functional models, such as sdram or spi memories could run this way.

Having bit-width propagate from inputs through components to outputs would be amazing

Wires can be joined and split by name from what is visually a single wire, and a single port can take a bundle and will make hidden ports on the subcircuit for just the bundled signals actually used inside the circuit

For example all control signals could be bundled, and split off in each subcircuit where it's used

A verilog design should be compilable into json with yosys and then be imported / synced with the circuit in digilogic

The components and wires will need some sort of automatic layout, like graphviz or ELK. Best effort is fine, manual fixup can be done after.

When viewing or editing subcircuits, they should open in tabs rather than separate windows. There is a separate issue for viewing two tabs at once

Ability to load a dynamic library with code that emulates a subcircuit in a more efficient manner during simulation. Should be easily toggled on and off. For example a gate level simulation of a processor could have a higher level emulator of that processor run instead in order to speed up the simulation.

If we implement propagation delays, calculate critical path and/or timing reports

It will be much slower to simulate propagation delays but would be invaluable, so would be nice if it could be optionally turned on and off

Potentially this would be via the verilog / yosys support

In Digital, because labels are inside components, there is a lot of pressure to have short names to keep components smaller. Figure out a design that doesn't have this pressure. May require some experimentation.

Value Change Dump, can be viewed in gtkwave

Sometimes its useful to see two circuits at once for reference, copy paste between them, etc. Support split screen and viewing at least two circuits side by side

FST is like VCD but produces smaller files and can be faster to produce and load, but is more complex to implement than VCD

Memory components should support optional input and/or output registers, separated or tristate data ports, etc. Any memory config in yosys supported fpgas and common SRAMs should be supported.

SDRAM and SPI memories could be supported via functional models loadable from dynamic libraries or perhaps iverilog simulation.

Yosys can import json and further optimize and synthesize it. Might be easier than generating verilog.

An imported KiCAD schematic can reimport over top in a way that allows keeping the digilogic version up to date with the KiCAD version

Only a subset of components would be importable, but stub subcircuits could be generated for components that aren't supported