Comments (1)
Fixed by #32.
from riscv-isa-sim.
Related Issues (20)
- mcontrol6.timing bit is set HOT 4
- Counter-intuitive MMIO device arguments behavior HOT 3
- reading mtinst gives illegal instruction exception HOT 1
- Spike setting VTYPE to 0x8000000000000000 for e16 mf8 HOT 1
- How can I read content from a file and use it as input for an ELF file HOT 4
- misa is not printed by the instruction csrrci HOT 1
- satp written with an unsupported MODE should have no effect HOT 7
- mstatus.fs cannot be written as initial HOT 2
- spike doesn't update sepc and stval in virtual address mode HOT 5
- Why misaligned store will raise store/amo access fault at the function store_slow_path? HOT 3
- Zfa extension instruction fcvtmod_w_d behavior conflict with sail model on too large/ too small boundary HOT 2
- Parse Zve/Zvl to determine RVV settings, instead of --varch HOT 1
- Build fails with "error: 'L_tmpnam' was not declared in this scope" HOT 4
- for vl=0 does vfredsum need to make vd[0]=vs1[0]? HOT 1
- Facing Issue running Zvbb RVV Cryptography Instructions HOT 3
- vmv1r.v instruction's behavior HOT 1
- Vector Widening Integer Multiply-Add Instructions - not working HOT 2
- fatal error: config.h: No such file or directory HOT 8
- assert failed in vectorUnit.cc from 71line. T&vectorUnit_t::elt(reg_t,reg_t,bool)[with T=long unsigned int; reg_t=long unsigned int]: Assertion '(VLEN>>3)/sizeof(T)>0' failed. HOT 3
- issue in counting numbers of instructions HOT 1
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