This repo is designed to wrap Flopoco FP operators into modules with parameterizable latency and also provide matching, drop-in-replacements that do not use the Flopoco-generated VHDL-code but instead use SystemVerilog and a C implementation for the actual math, which is faster to simulate and works in Verilator to Simulate (which does not support VHDL).

Operators use the Flopoco-specific format that is 2 bits wider than the IEEE-based formats and is simpler to decode. As the C-implementations do support subnormals and operate on IEEE formats, they are wrapped with conversions from and to the Flopoco-specific format with 0 latency, that will strip away unsupported values & flags. Currently this repo only includes single-precision operators as that is all I needed.

The actual Flopoco VHDL implementations are missing from this repo. They can be generated by Flopoco (see Wiki article for example). As Flopoco optimizes for a specific target FPGA-architecture, the modules I built (and whose names are hardcoded in files like CMakeSources.txt) are only optimal to my specific target-FPGA (which is actually not supported by Flopoco, so I used similar architectures as targets) and probably only synthesizable on Xilinx 7-series FPGAs. Also avoids any licensing issues with Flopoco.

Ideally, this repo would be enhanced by scripts that can generate operators on demand for the needed target architecture or a file-name structure that allows to store all possible targets next to each other. Since I have only one target platform, I have not spent the time to implement this part and simply generated only the operators suitable for my specific needs. This main point of making this repo available is the drop-in replacements that allows simulating it in Verilator.