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attribute-parser

C++ based basic HTML parser

autopen

Autopen is an open-source toolkit designed to assist security analysts, manufacturers, and various professionals to detect potential vulnerabilities in vehicles.

bash-latex-resume

This bash script auto generates my resume in pdf format. A bash script asks questions and creates a .tex file according to the answers. The .tex file is compiled using pdflatex into a pdf that shows my resume.

bcd-adder

An 8-bit Binary-Coded-Decimal (BCD) adder was implemented and tested using Verilog HDL.

cherno-instrumentor

Instrumentor for C++ that outputs json for Chrome tracing

colabs

consecutive-ones-detector

A FIFO pipeline based consecutive ones detector, developed in Verilog, using structural data flow model

crypto-algorithms

Basic implementations of standard cryptography algorithms, like AES and SHA-1.

ctf

CTF Writeups

dotfiles

my config files for various utilities

fractional_knapsack

algo practice

hmac

A command line tool for computing SHA256 HMACs

macan

Message Authenticated CAN library & tools written in C

prext

PREXT is a unified and extensible framework that simulate pseudonym change schemes (i.e., privacy schemes) in VANET.

py-grep

Python based pattern searching tool to run on Windows command line and save development time

raash1d.github.io

GitHub website

sankey-representation

smart-traffic-light-controller

A Mealy Finite State Machine (FSM), developed in Verilog, designed to control traffic lights at a crossroad having a major road (main road) and a minor road (side road).

stepper-motor-fsm

An FSM mimicking the functionality of a stepper motor. Direction controls decide the direction of rotation and the angle of rotation.

sublime-text-user-settings

My user settings for sublime text 3

tiny-aes128-c

Small portable AES128 in C

vasp

VASP is a framework to simulate attacks on V2X networks. It works on top of the VEINS simulator.

veins

Veins - The open source vehicular network simulation framework.

washing-machine-controller

A synthesizable Verilog RTL implementation of a finite state machine to control a complete cycle of an automatic washing machine with asynchronous reset to idle state in case of a loss of power.

yolov7

Implementation of paper - YOLOv7: Trainable bag-of-freebies sets new state-of-the-art for real-time object detectors