Comments (6)
There is no solution for this issue using the existing procedure for Verilog-A devices. I am planning to add new Verilog-A device that will act like SPICE file device and will not require the JSON files. But don't expect this feature to be implemented in the near future because of low demand and high time effort.
You can use the following workaround.
- Compile the VA file from CLI outside Qucs-S using OpenVAF
- Specify the OSDI path using the spiceinit script.
- Put .MODEL on schematic
- Put the SPICE generic (Z) device referencing letter N and specify the proper model name for it
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The file usually has a flag of 0/1 or 1/-1 that determines n or p. One could add a line that sets the flag and create two files.
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It is not possible to attach two JSON *.sym
files to one *.va
file using the existing workflow. Wait until the Verilog-A devices will be rewritten without need to use JSON or use the workaround. I don't promise a quick fix for this.
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One could create two files and add a line that sets the flag.
I don't use Verilog myself...
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@ra3xdh : Don't know your concept. But at the moment it is a bit cumbersome that each instance get his own model fixed burned in the netlist. This prevent to include library files with .model cards for each device construction and type. This concept can sufficient for usual rf circuits but not for analog and mixed-signal circuits.
Another topic is the separation of instance and model parameter. The latest release of CMC VA models make more and more this distinction, whenever unfortunately some models allow double usage - model and device parameter. I think it should considered to take care for that in the future.
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The issue is not resolvable using the current way of Verilog-A devices support using the JSON files. Use the proposed workaround with SPICE generic device and modelcard. The situation will improve after implementation of #343 Don't expect a quick fix here. Closing for now.
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Related Issues (20)
- Replace FreeHDL by GHDL HOT 1
- Get rid of digital simulation wrapper scripts
- Active Filter Tool confusion HOT 1
- Device falls out of grid after rotation HOT 3
- Update Matching Tool to Qucs 0.0.20 Version HOT 2
- Regulators.lib and ngspice issues with LM317 spice models HOT 14
- LDMOS simulation froze Windows HOT 12
- Greyed out choices in Spice .Model HOT 2
- Nutmeg Scripting for Power Amplifier Wingspread Analysis HOT 4
- QUCS-S 2.1.0: Tuner Slider Bug HOT 2
- Backward schematic compatibility HOT 4
- Schematic Editor: Deactivate/Activate of Blocks Does Not Work Consistent HOT 2
- Tuner Slider Does Not Handle Numbers and Units in .PARAM Block Correctly HOT 1
- Provide an option to disable transient model for RF port HOT 9
- Add entry field for external model for Verilog-A HOT 5
- New Regulators.lib HOT 1
- False error reported? HOT 6
- Qucs-S 24.1-7df03e9 - Yet Another Tuner Slider Bug HOT 3
- net name restrictions HOT 1
- Tuner Slider GUI Window Size Scaling Issue HOT 6
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