#6

• clock delay alignment
• frame packing/unpacking
• checksum
• multi-spi

• identification
• error counter readout
• delay readout

There is no licence file for this repository and no licence specified in a header in each .py file, which means that by default there are no rights granted (other than the ones in GitHub's terms). This is an issue for making legal use of and modifications to the design.

Could a LICENSE file or similar be added?

• CIC inteprolator
• Cubic (fourth order interpolator) (-53 dB sidelobes)
• Channel sequencer with two interpolators each handling 16 channels
• per channel configurable rate change up to 1<<16
• per channel configurable gain compensation in powers of two
• ARTIQ coredevice driver

Bug Report

Fixes in gateware for use of Fastino

One-Line Summary

Three issues with using Fastino that might be possible to fix in gateware

Issue Details

Steps to Reproduce

1. Step 1. Switch on a system with Kasli + Fastino, ARTIQ7
2. Step 2. Look at Fastino output (e.g. one channel on a scope)
3. Step 3. Program different voltages onto the Fastino channel and capture the moment when the voltage is set on a scope

Expected Behavior

• all Fastino channels going to 0 V at startup
• no negative spike when setting the voltages

Actual (undesired) Behavior

• We are using several Kaslis with one Fastino each, using ARTIQ7. We've identified three issues that prevent us from efficiently working with the system, and it seems they may be fixable by gateware changes:

• On startup, all channels go to their maximum negative voltage (so around -10 V) - it would be preferable for them to go to 0 V instead
• When running a script which sets a voltage on one or more channels, the affected channels produce a negative spike (basically trying to go to the negative maximum as far as I can tell) before ramping up to the desired voltage (see a random image of the scope attached, can provide better pictures if needed). This happens only for the first voltage one sets in a script, so we are assuming that it comes from the Fastino init procedure - instead of going to 0 V when being initialized, it seems to be going to 0 m.u. It would be great if it could go to 0 V instead.
• What has changed from ARTIQ6 to ARTIQ7: this negative spike described above is now happening every time one runs the script - with ARTIQ6 it was only happening the first time one was running a script after power-up.
  

• As an info: Mikolaj was starting to look into these issues and said there is good hope for a gateware fix, but has now asked me to create an issue here.

Your System (omit irrelevant parts)

• Operating System: Windows 10, using Conda

• ARTIQ version: ARTIQ v7.8006.bbb2c75.beta

• Version of the gateware and runtime loaded in the core device:
  [ 0.003934s] INFO(runtime): software ident 7.8019.f89275b.beta;kasli-aegis-5tc1
  [ 0.011344s] INFO(runtime): gateware ident 7.8019.f89275b.beta;kasli-aegis-5tc1

• If using Conda, output of conda list:
  conda_list_output2.docx

• Hardware involved: Kasli version 2.0, Fastino version 1.2

• head/tail features
• settle/clear/reset behavior
• order and rate change behavior

https://m-labs.hk/artiq/manual-beta/core_drivers_reference.html#artiq.coredevice.phaser.Miqro.set_window_mu

c.f.
https://github.com/quartiq/miqro-sim#simulator-output

Both monitoring and injection in Fastino would be relatively simple from a technical perspective. The state is already mirrored in the RTIO phy, the protocol is trivial, and there is no chance for bus contention.