Quentin Ducasse's Projects
:wrench: Basic standalone vhdl utilities (counter, ual, ram, etc.)
š Selenium-based bib finder for scientific articles
š Sources for my blog https://qducasse.github.io
:boat: Java-based harbor simulator with client/server TCP mechanics.
āļø Airport checkin simulation in Java
š Chisel implementation of simple RIMI verifications
Neural Networks topologies run against the CIFAR10 dataset in PyTorch
š Stack-VM in C for Lox (craftinginterpreters)
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
š Source and article of my MSC's Dissertation Thesis
:flight_departure: Air traffic controller simulator using simulated planes/radars. Objective - impact of a compromised radar and FDI attack on state estimators
Dataflow compiler for QNN inference on FPGAs
šØ Base for an ACM/IEEE article
šŗ Interpretation loop and JIT code generator to benchmark RISC-V isolation mechanisms
:triangular_flag_on_post: Bookmark setter and quick traveller for our terminal
š Scripts for a quick setup of an OSX working environment
š Python-based parser for Issuu files
Assembly tests following the JITDomain instruction-level domain isolation principle
š” Notes and bib manager (articles are mostly related to language virtual machines or runtime engines)
š Tutorial on the LLVM C bindings
LLVM C bindings from Pharo
š¼ Pillar dummy book with tagged commits
:slot_machine: 32-registers Instruction Simulator. Assembler computation and execution on a simulated 32-register system.
š» Mini browser performing HTTP requests and displaying site content
:film_strip: Python-based lexer and parser generator from an EBNF grammar.
š Masters dissertation references
š§ Benchmark facility to train networks on different datasets for PyTorch/Brevitas
This is the VM used by Pharo
Pharo bindings to the LLVM disassembler
Pharo bindings to the Unicorn machine code simulation library