The tech_cells_generic from pulp-platform

Add cluster_clock_inverter.sv and pulp_clock_mux2.sv in repo

Hello @zarubaf, @meggiman, @niwis (sorry I do not know who is the repo leader)

I have a legacy issue with tech_cells_generic repo.

tech_cells_generic repo does not contain cluster_clock_inverter.sv and pulp_clock_mux2.sv anymore !

In CVA6 project, dmi_jtag_tap module instantiates cluster_clock_inverter and pulp_clock_mux2 modules and I would be pleased to use the new tc_srams module. Could you add the cluster_clock_inverter.sv and pulp_clock_mux2.sv cells in the last tech_cells_generic version ?

Thanks

SRAM implementation and generalisation

Problem

The current tc_sram wrapper does not generalize to more than one clock and the ports always come with read and write capabilities. That is a bit too limiting for the memories that are usually available in modern techs.

Furthermore I think it would be nice to capture all the behavior of the memory in a commonly understandable format (json, protofbufs) so that we can extend and automatize the generation of the SRAM instantiations.

SRAM Request Format

This is my straw-man proposal:

{
    "$schema": "http://json-schema.org/draft-07/schema#",
    "$id": "http://pulp-platform.org/snitch/memory.schema.json",
    "title": "memory_schema",
    "description": "Generic Schema to describe properties of SRAMs.",
    "type": "object",
    "required": ["num_words", "data_width"],
    "properties": {
        "description": {
            "type": "string",
            "description": "Optional description."
        },
        "num_words": {
            "type": "integer",
            "description": "Number of words in data array."
        },
        "data_width": {
            "type": "integer",
            "description": "Data width in bits."
        },
        "initialization": {
            "type": "string",
            "description": "(Optional) initialization of memory.",
            "enum": ["none", "ones", "zeros", "random"],
            "default": "none"
        },
        "implementation": {
            "description": "(Physical) Implementation details.",
            "type": "object",
            "properties": {
                "type": {
                    "type": "string",
                    "description": "(Optional) Implementation type. Register file or SRAM.",
                    "enum": [
                        "rf",
                        "sram"
                    ]
                },
                "optimization": {
                    "type": "string",
                    "description": "(Optional) Optimization hint. Should this be tuned towards speed or density.",
                    "enum": [
                        "perf", "density"
                    ]
                }
            }
        },
        "independent_clocks": {
            "type": "boolean",
            "description": "Each port has an independent clock associated (multi-clock memories).",
            "default": false
        },
        "ports": {
            "type": "array",
            "items": {
                "type": "object",
                "description": "Description of a port of the memory array.",
                "additionalItems": false,
                "minItems": 1,
                "properties": {
                    "read": {
                        "type": "boolean",
                        "description": "Enable read capabilities on port.",
                        "default": true
                    },
                    "read_latency": {
                        "type": "integer",
                        "description": "Number of latency from read request valid to read data valid.",
                        "default": 1
                    },
                    "write": {
                        "type": "boolean",
                        "description": "Enable write capabilities on port.",
                        "default": true
                    },
                    "byte_width": {
                        "type": "integer",
                        "description": "Byte width in bits. In cas the byte width does not divide the data width the most significant byte will be smaller (i.e., truncated).",
                        "default": true
                    },
                    "byte_mask": {
                        "type": "boolean",
                        "description": "Has a byte mask, i.e., bytes can be written independently.",
                        "default": 8
                    }
                }
            }
        }
    }
}

I think in the future it can hold much more, such as BIST capabilities, physical design aspects (i.e., number of rails, preferred aspect ratio, etc.). Ideally, we would end up with a generation infrastructure for each technology that sanitizes the inputs for a given technology and generates the infrastructure.

Re-structure

I would furthermore propose that we split the tc_sram into a tc_sram and tc_sram_core. The latter just containing the memory array (i.e., the thing that will be replaced by tech-specific stuff). That will also allow us to implement (or provide an implementation) of the core as flip-flops or latches. That is something we can also provide as open-source.

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Add cluster_clock_inverter.sv and pulp_clock_mux2.sv in repo

SRAM implementation and generalisation

Problem

SRAM Request Format

Re-structure

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