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We probably need to think about generating a couple of different systems in occamygen.py.
I can at least think about two in that context:

1. RTL Sim
2. FPGA
3. (ASIC in the private wrapper repo)

I think we have all the necessary ingredients for this. What is missing is:

• Create a second(/third) configuration file. Using jsonref we could also share the cluster configuration between the system configuration.
• Generate the RTL into dedicated directories
• (Manually) adapt the Bender.yml to include the appropriate files.

Actually, maybe we can call the occamy_cluster_pkg::sram_cfgs_t something like occamy_cluster_pkg::sram_cluster_cfgs_t and the occamy_pkg::sram_cfgs_t something like occamy_pkg::sram_occamy_cfgs_t?

Originally posted by @GiannaP in pulp-platform/snitch#303 (comment)

Make sure that the params.json can be changed directly in Occamy, rather than taking the configuration of the snitch_cluster dependency

Currently, all AXI crossbars in occamy are configured with master port 0 as default slave:
https://github.com/pulp-platform/snitch/blob/49346c18504c06df088bf86a21e78f7ebc31d9ea/util/solder/solder.py#L1364-L1365

For the top-level crossbars, it might make sense to disable the default slave and return a DEC_ERROR when accessing an unmapped memory region instead.

The verilator testbench is faster for cycle-accurate software benchmarks than VCS/VSIM simulators. Occamy is not yet fully verilator compatible. Verilating this many cores will require a lot of RAM and will likely not work.

This was the motivation to enable hierachical mode inside the Snitch cluster. Current effort can be seen in the verilator-hierachical branch.

Problems

• hierachical designs don't support parameter type parameters. This was mitigated by adding a wrapper around snitch_cc and passing the structs by their bit with and re-generating the structs before instantiating snitch_cc

Current progress

The model compiles but the first instructions to the FPU subsystem are not retired

fcvt.d.w ft0, zero             #; ac1  = 0
fcvt.d.w ft1, zero             #; ac1  = 0

The VSIM testbench works with the modifications enabled (adding ``define VERILATORand runmake bin/snitch_cluster.vsim`). Instructions offloaded to outside `snitch_cc` work too (`div/mul`). The `fcvt` instruction is offloaded to the FPU-SS that resides inside `snitch_cc` which due to the hierarchical mode cannot be inspected in the generated VCD.

This issue should serve as an entry-point for someone interested in picking this up again.