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License: Other
PolarFire SoC hart software services
License: Other
Current version of HSS is still using OpenSBI v0.6 which is quite old.
Is there any plan to upgrade to a recent version of OpenSBI that supports HSM, etc?
When I am going to burn HSS through boot mode 1, I encountered the following problem.
[ Generate bitstream... ]
The eNVM configuration has the following validation errors:
The ENVM configuration has the following errors:
Client 'bootmode1': Unable to open memory file 'hss-envm-wrapper.hex'.
Error: Failed to generate eNVM EFC from CFG. Return code = 1
Error: generate bitstream failed, exiting...
Error: check the log for errors and refer to D:/Microchip/SoftConsole-v6.5//extras/mpfs/readme.txt if necessary
[ Finished (failure) ]
I have checked the path of fpgenprog.exe. Has anyone encountered such a problem?
File "tools/compression/hss-deflate.py", line 44
def deflate(data: bytes, compression_level: int = 9) -> bytes:
^
SyntaxError: invalid syntax
make: *** [envm-wrapper/Makefile:95: Default/hss-l2scratch.bin.deflate] Error 1
"make all" terminated with exit code 2. Build might be incomplete.
Confirmation - below is expected solution against HSS Build Error on SoftConsole v2021.1 in terms of Kconfiglib ?
[Solution]: Adding "genconfig.py" path to PYTHONPATH variable
PYTHONPATH=/home/${USER}/.local/lib/python3.6/site-packages:${PYTHONPATH}
export PYTHONPATH="/home/$USER/.local/lib/python3.6/site-packages:${PYTHONPATH}"
using cross-building from a debian-buster x86_64 the build fails on crt.S
$ make CROSS_COMPILE=riscv64-linux-gnu-
crt.S: Assembler messages:
crt.S:23: Error: unknown pseudo-op: .attribute' crt.S:24: Error: unknown pseudo-op:
.attribute'
$ riscv64-linux-gnu-gcc -v
gcc version 8.3.0 (Debian 8.3.0-2)
When attempting to build BOARD=icicle-kit-es with the current version of
https://github.com/riscv/riscv-gnu-toolchain (gcc 10.1.0), it bombs out in
baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/system_startup.c with:
baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/system_startup.c:115:25: error: array subscript -64 is outside array bounds of 'long unsigned int[1]' [-Werror=array-bounds] 115 | hls = (HLS_DATA*)((uint8_t *)&__stack_bottom_h1$ | ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 | + (((uint8_t *)&__stack_top_h1$ - | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 | (uint8_t *)&__stack_bottom_h1$) * hard_idx) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 118 | - (uint8_t *)(HLS_DEBUG_AREA_SIZE)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/mss_hal.h:70, from baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/system_startup.c:32: baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/system_startup.h:41:22: note: while referencing '__stack_bottom_h1$' 41 | extern unsigned long __stack_bottom_h1$; | ^~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors
I have the Polarfire ES kit. I2C driver exists in the HSS, but it looks like it's unused. I use the I2C in my own code, but I cannot get it to work. Any register write into i2c registers starting from I2C_A_LO / I2C_B_LO (0x2010A000 / 0x2010B000) as well as I2C_B_LO / I2C_B_HI is lost, meaning a readback shows it's all zeroes although I write the enable bit, slave address etc. According to MSS configurator and the HSS .xml file, I2C1 should be enabled in the board.
Also I make sure these bits are properly configured:
Am I missing something regarding the I2C?
Several source files under ./baremetal/ are using UTF-8 encoding (over ASCII) with no real technical justification,
the problem files may be listed with the following command:
find . -type f -name \*.[ch] | xargs file | grep UTF
Apparently, non-ASCII characters are used for an apostrophe, a bullet in lists, may be something else.
Some source files have blanks at the end of line and empty lines at the end (e.g. ./services/mmc/mmc_api.c)
Apologies for naive question - I'm new to FPGA kitchen. I have had the board for a while, but decided to give it a spin only now.
So basically this:
...
2 GB LPDDR4 x 32
...
HSS_Boot_PMPSetupHandler(): Hart1 setup complete
HSS_OpenSBI_Setup(): MTVEC switching from 20220230 to 20220100
U-Boot 2020.01 (Aug 11 2020 - 21:55:51 +0000)
DRAM: 1 GiB
...
hart-software-services/misc/hss_memtest.c
Line 211 in 078ce16
4.The DDR chip is a Micron D9WHZ, that is:
MT53D512M32D2DS-053 WT:D D9WHZ 16GB
How much RAM can I address on this device?
Please complete this checklist before filing an issue:
hss-payload-generator
wrong or not.I am trying to pass some ancillary data corresponding to a device tree using the following hss-payload-generator
config:
set-name: 'PolarFire-SoC-HSS::U-Boot'
hart-entry-points: {u54_1: '0x90200000', u54_2: '0x90200000', u54_3: '0x90200000', u54_4: '0x90200000'}
payloads:
src.bin: {exec-addr: '0x90200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_s, ancilliary-data: mpfs-icicle-kit.dtb}
The expected behavior for me is that the address for the device tree is stored in each hart's scratch->next_arg1
, and indeed this is the case for most of OpenSBI init. However, in sbi_domain_finalize
, it seems that the boot hart's next_arg1
is set to NULL
, corresponding to the src.bin
domain's next_arg1
. From my debugging, it seems that the cause of this issue is the mpfs_domains_register_boot_hart
function which initializes the hart_ledger
for the boot hart (the hart_ledger
is later used is mpfs_domains_init
to initialize the OpenSBI domains specified in the configuration, including src.bin
). One parameter to this function is void *pArg1
, which should hold the address of the desired ancillary data. However, mpfs_domains_register_boot_hart
is itself called in boot_setup_pmp_onEntry
, which is a function called very early on in the boot process. It is called so early, in fact, that the boot image has not really been parsed yet -- no ancillary data has been extracted yet and therefore pArg1
will be NULL
, which causes the src.bin
domain to have NULL
as its next_arg1
.
I will note that when the harts hit sbi_init
, the value in scratch->next_arg1
is correct -- however, the cold-booting hart eventually calls sbi_domain_finalize
which trashes the value in all of the harts' scratch->next_arg1
.
I think the most straightforward option to address this (in my opinion) is to defer the call to mpfs_domains_register_boot_hart
until after image parsing, to ensure that the ancillary data is correctly populated (maybe in boot_download_chunks_onExit
, which is currently empty). However, I'm not familiar enough with the HSS architecture in order to know what the best option is.
I might also be using the hss-payload-generator
incorrectly? I'm unsure.
In the file: baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_sgmii.c:
There's a duplicate line, should the other be MSS_PERIPH_MAC1 instead of MSS_PERIPH_MAC0?
(void)mss_config_clk_rst(MSS_PERIPH_MAC0, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON);
(void)mss_config_clk_rst(MSS_PERIPH_MAC0, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON);
GEM_A_LO->network_config |= (0x01U << 10U) | (0x01U << 11U); /* GEM0 */
GEM_B_LO->network_config |= (0x01U << 10U) | (0x01U << 11U); /* GEM1 */
Packaging the hss-payload-generator for a Linux distro should include all source code needed to create the distributed binaries.
Could you, please, make the source of baremetal.elf available? Should be a file helloWorld.c.
Ideally you would add a Makefile target to cross compile it.
When using GDB to debug HSS on QEMU, GDB complains:
[Errno 2] No such file or directory: 'folk/bmeng/work/git/polarfire-soc/hart-software-services/crt.S'
It's weird that the path is missing the leading /
in the DW_AT_comp_dir
field in the DWARF information, as the actual path for the HSS source is /folk/bmeng/work/git/polarfire-soc/hart-software-services
.
Please complete this checklist before filing an issue:
The switch_demux_using_fabric_ip() function always gets called at boot time inside the mmc_init_sdcard() function.
This creates a problem for boards which do not feature an external switch. The FPGA design also does not contain additional fabric logic to control it.
We observe a problem on the Discovery Kit when using a minimalistic FPGA design (FIC_3_PERIPHERALS_0 and FIC_0_PERIPHERALS_0 removed from the reference design).
With that design change the board would not boot from SD Card.
The HSS Boot is stuck at "Attempting to select SDCARD ..." and HSS is stuck in an endless restart cycle.
Commenting out Line #168 in hart-software-services/services/mmc/mmc_api.c resolved the problem and SDCARD boot is working again for that board+fpga design combination.
Please make sure to add all the information needed to understand the bug so that someone can help. If the info is missing we'll add the 'Needs more information' label and close the issue until there is enough information.
"MSS Only" FPGA Design (FIC_0_ / FIC_3_PERIPHERAL removed from 2024.04 MPFS-DISCO-KIT Refdesign):
Code, switching the IO mode between e.MMC and SDcard interfaces (services/mmc/mmc_api.c), writes per-defined constants into the IOMUXx_CR (x=1, 2, 6) registers and overwrites settings for unrelated pads, making them non-functional.
Additionally, the documentation for the IOMUXx_CR registers seems to be incomplete, this issue is reported via Microsemi SoC support portal under case # 493642-2837732661
Hi,
I got a issue booting with QSPI.
I have ICICLE-KIT & VIDEO-KIT and both doesn't work.
Enabled CONFIG_SERVICE_QSPI & CONFIG_SERVICE_QSPI_MICRON_MQ25T.
But i got only this log
[6.157924] PolarFire(R) SoC Hart Software Services (HSS) - version 0.99.37-unknown
MPFS HAL version 2.2.104 / DDR Driver version 0.4.023 / Mi-V IHC version 0.1.1 / BOARD=mpfs-icicle-kit-es
(c) Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions.
incorporating OpenSBI - version 1.2
(c) Copyright 2019-2022 Western Digital Corporation.
[6.193251] Build ID: c505aa96a2f0b2c340878848b5c900273c58f6d3
[6.200794] Built with the following tools:
[6.224855] NOTICE: Running from L2 Scratchpad
[6.231061] Serial Number:
6a1f88bf35e83fbfa3e9cf671615e74900000000000000000000000000000000000000000000000000000000000000000000
[6.245001] Segment Configuration:
Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000
Cached: SEG0_1: offset 0x1000000000, physical DDR 0x00000000
Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x00000000
Non-cached: SEG1_3: offset 0x1400000000, physical DDR 0x00000000
Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x00000000
Non-cached WCB: SEG1_5: offset 0x1800000000, physical DDR 0x00000000
[6.289972] L2 Cache Configuration:
L2-Scratchpad: 4 ways (512 KiB)
L2-Cache: 8 ways (1024 KiB)
L2-LIM: 4 ways (512 KiB)
[6.305918] DDR-Lo size is 32 MiB
[6.310596] DDR-Hi size is 1888 MiB
[6.334327] Please ensure that jumpers J34/J43 are correct for 1.8V MMC voltage...
[6.343875] Attempting to select SDCARD ... Failed
[6.403984] Attempting to select eMMC ... Passed
[6.674844] Initialized Flash (JEDEC 000000)
[6.680382] HSS_QSPIInit() returned 0
Press a key to enter CLI, ESC to skip
Timeout in 1 second
.
[7.691454] CLI boot interrupt timeout
[7.696419] Initializing Mi-V IHC
[7.700906] Initializing IPI Queues (6056 bytes @ a02fb88)...
[7.708068] Initializing PMPs
[7.712173] Initializing Boot Image ...
[7.717234] Trying to boot via QSPI ...
[7.741512] Initialized Flash (JEDEC 000000)
[7.747049] Trying to boot via MMC ...
[7.752014] Attempting to select SDCARD ... Failed
[7.812123] Attempting to select eMMC ... Passed
[8.65501] Preparing to copy from MMC to DDR ...
Actually, There is no problem accessing QSPI in kernel after MMC boot.
So i kind of doubt HSS doesn't support QSPI function yet.
Please let me know what i miss.
Thanks.
[Error message on SoftConsole v2021.1]
ERROR - ELF file linked incorrectly. The boot vector for the eNVM must be between "0x20220000" and "0x2023FFFF" but the selected ELF file "hss-l2lim.elf" has boot vector "0x08000000". Check the linker script used to link the program.
[Operation]
[Inquiry]
From 2021.08, what addition operation is required to program HSS into eNVM through SC v2021.1 ?
Hello,
Thank you for the great tools.
I'm now evaluating bin2chunks (commit 078ce16) to boot hart 1 and 2 (U54_1 and U54_2) as
$ ./tools/bin2chunks/bin2chunks 0x08020000 0x8020000 0 0 32768 payload.bin 1 3 some.bin 0x08020000 2 3 /dev/null 0
However, this causes an assertion error in validate_privmode_()
.
I have applied the following changes and it now looks working fine.
diff --git a/tools/bin2chunks/bin2chunks.c b/tools/bin2chunks/bin2chunks.c
index 32e6e2b..401b2cd 100755
--- a/tools/bin2chunks/bin2chunks.c
+++ b/tools/bin2chunks/bin2chunks.c
@@ -474,7 +474,7 @@ static void validate_owner_(int owner) {
}
static void validate_privmode_(int privmode) {
- assert((privmode >= PRV_U) && (privmode <=PRV_S));
+ assert((privmode >= PRV_U) && (privmode <=PRV_M));
}
char imageNameBuf[1024] = "";
@@ -535,7 +535,7 @@ int main(int argc, char **argv)
printf(" - hart owner is >>%d<<\n", ownerArray[i]);
privMode[i] = strtol(argv[argIndex++], NULL, 10);
- validate_privmode_(ownerArray[i]);
+ validate_privmode_(privMode[i]);
printf(" - privMode >>%d<<\n", privMode[i]);
pFileNameArray[i] = argv[argIndex++];
Could you please check the code?
Regards,
Atsushi Yokoyama
Hi,
We are relying on the watchdog mechanism to have the board rebooted in case of system freeze (Linux in our case).
That feature used to work as expected on the HSS 0.99.26 (together with Reference design 2021.11 and Polarfire Yocto BSP 2021.11) on an IcicleKit, in the sense that the board did get successfully restarted on watchdog timeout (in case it was not refreshed).
We however noticed since upgrading to HSS 0.99.33 // Ref Design 2022.09 // Yocto BSP 2022.09 that HSS fails to restart the board on first watchdog timeout signal.
It eventually manages to restart the board, but only after having received 9 more watchdog timeout signals (as the log shows below). If the watchdog runtime duration is set to 30 seconds and the watchdog is not actively refreshed, the board therefore ends up being effectively rebooted only after about 300 seconds instead of 30 seconds (that is, at the end of 10 watchdog timeout signals).
Could it be a regression in the HSS ?
Here is a set of Linux commands that may be used to reproduce the issue, using the devmem2 linux command line tool.
This sets up the U54 watchdog 1 with the maximum runtime duration (about 30 seconds) and let it expire.
The expected outcome is that the board gets rebooted immediately on watchdog timeout.
# -- Setup and start watchdog 1 --
# Set WATCHDOG1.MVRP to about 75% of max duration
devmem2 0x20101010 w 0x00BFFFF4
# Set WATCHDOG1.TRIGGER to its max value
devmem2 0x20101014 w 0x00000FFF
# Set WATCHDOG1.RUNTIME to max duration (about 30 seconds)
devmem2 0x2010100C w 0x00FFFFF0
# Set WATCHDOG1.CTRL to (4:forbidden_enabled + 1:wdog_irq_enabled + 0:mvrp_irq_enabled)
devmem2 0x20101004 w 0x13
# Write into WATCHDOG1.REFRESH to start watchdog 1
devmem2 0x20101000 w 0xDEADC0DE
# -- Check watchdog 1 state --
# Check WATCHDOG1 counter value
devmem2 0x20101000 w
# Check WATCHDOG1 status
devmem2 0x20101008 w
Here is below the HSS log, taken from the first watchdog timeout trigger event.
Notice the lines 'Watchdog has triggered - 10' appearing 10 times, roughly every 30 seconds.
The system finally gets restarted at the [419.13129] time mark, after 9 failed attempts.
Thanks for your inputs.
[160.253111] Watchdog has triggered - 10
[160.258718] Boot image passed CRC
[160.263683] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[160.271009] Boot image passed CRC
[160.275974] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[160.283300] Boot image passed CRC
[160.288265] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[160.295590] Boot image passed CRC
[160.300555] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[160.307812] boot_service(u54_1) :: [Init] -> [SetupPMP]
[160.314877] boot_service(u54_2) :: [Init] -> [SetupPMP]
[160.321943] boot_service(u54_3) :: [Init] -> [SetupPMP]
[160.329008] boot_service(u54_4) :: [Init] -> [SetupPMP]
[160.336074] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[160.345335] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[160.353547] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[160.361758] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[160.369969] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[160.378181] u54 State Change: [Booting] [Booting] [Booting] [Booting]
[160.387729] boot_service(u54_1) :: [SetupPMPComplete] -> [ZeroInit]
[160.395940] boot_service(u54_2) :: [SetupPMPComplete] -> [ZeroInit]
[160.404151] boot_service(u54_3) :: [SetupPMPComplete] -> [ZeroInit]
[160.412362] boot_service(u54_4) :: [SetupPMPComplete] -> [ZeroInit]
[160.420574] boot_service(u54_1) :: [ZeroInit] -> [Download]
[160.428021] boot_service(u54_2) :: [ZeroInit] -> [Download]
[160.435469] boot_service(u54_3) :: [ZeroInit] -> [Download]
[160.442916] boot_service(u54_4) :: [ZeroInit] -> [Download]
[160.450363] boot_service(u54_1)::Processing boot image: "u-boot.bin"
[160.458384] boot_service(u54_2) :: [Download] -> [Idle]
[160.465449] boot_service(u54_3) :: [Download] -> [Idle]
[160.472515] boot_service(u54_4) :: [Download] -> [Idle]
[160.535506] boot_service(u54_1) :: [Download] -> [OpenSBIInit]
[160.543240] boot_service(u54_1)::u54_2:sbi_init 0x1000200000
[160.550496] u54 State Change: [Booting] [SBIWaitForColdboot] [Booting] [Booting]
[160.561094] boot_service(u54_1)::u54_3:sbi_init 0x1000200000
[160.568351] u54 State Change: [Booting] [SBIWaitForColdboot] [SBIWaitForColdboot] [Booting]
[160.579999] boot_service(u54_1)::u54_4:sbi_init 0x1000200000
[160.587256] u54 State Change: [Booting] [SBIWaitForColdboot] [SBIWaitForColdboot] [SBIWaitForColdboot]
[160.599955] boot_service(u54_1) :: [OpenSBIInit] -> [Wait]
[160.607307] boot_service(u54_1)::u54_1:sbi_init 0x1000200000
[160.614563] boot_service(u54_1)::Checking for IPI ACKs: - -
[160.621724] boot_service(u54_1)::Checking for IPI ACKs: ACK/IDLE ACK
[160.629744] boot_service(u54_1) :: [Wait] -> [Idle]
[160.636428] u54 State Change: [Fatal] [SBIWaitForColdboot] [SBIWaitForColdboot] [SBIWaitForColdboot]
[171.471403] loop 15000000 took 4736 ticks (max 64391704 ticks)
[188.886069] Watchdog has triggered - 10
[188.891677] Boot image passed CRC
[188.896642] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[188.903968] Boot image passed CRC
[188.908933] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[188.916259] Boot image passed CRC
[188.921224] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[188.928549] Boot image passed CRC
[188.933514] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[188.940771] boot_service(u54_1) :: [Init] -> [SetupPMP]
[188.947836] boot_service(u54_2) :: [Init] -> [SetupPMP]
[188.954902] boot_service(u54_3) :: [Init] -> [SetupPMP]
[188.961967] boot_service(u54_4) :: [Init] -> [SetupPMP]
[188.969033] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[188.978295] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[188.986506] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[188.994717] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[189.02928] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[189.941063] boot_service(u54_1)::Timeout after 81321 iterations
[189.948892] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[189.956817] boot_service(u54_2)::Timeout after 81321 iterations
[189.964646] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[189.972571] boot_service(u54_3)::Timeout after 81321 iterations
[189.980401] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[189.988325] boot_service(u54_4)::Timeout after 81321 iterations
[189.996155] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[190.04080] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[190.28713] boot_service(u54_1) :: [Error] -> [Idle]
[190.35397] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[190.60031] boot_service(u54_2) :: [Error] -> [Idle]
[190.66714] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[190.91348] boot_service(u54_3) :: [Error] -> [Idle]
[190.98032] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[190.122666] boot_service(u54_4) :: [Error] -> [Idle]
[190.129445] loop 16711684 took 75219162 ticks (max 75219162 ticks)
[198.543377] loop 17500000 took 4755 ticks (max 75219162 ticks)
[217.519159] Watchdog has triggered - 10
[217.524766] Boot image passed CRC
[217.529731] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[217.537057] Boot image passed CRC
[217.542022] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[217.549348] Boot image passed CRC
[217.554313] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[217.561639] Boot image passed CRC
[217.566604] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[217.573860] boot_service(u54_1) :: [Init] -> [SetupPMP]
[217.580926] boot_service(u54_2) :: [Init] -> [SetupPMP]
[217.587991] boot_service(u54_3) :: [Init] -> [SetupPMP]
[217.595057] boot_service(u54_4) :: [Init] -> [SetupPMP]
[217.602122] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[217.611384] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[217.619595] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[217.627806] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[217.636018] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[218.573770] boot_service(u54_1)::Timeout after 81100 iterations
[218.581599] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[218.589524] boot_service(u54_2)::Timeout after 81100 iterations
[218.597354] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[218.605278] boot_service(u54_3)::Timeout after 81100 iterations
[218.613108] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[218.621033] boot_service(u54_4)::Timeout after 81100 iterations
[218.628862] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[218.636787] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[218.661516] boot_service(u54_1) :: [Error] -> [Idle]
[218.668295] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[218.693025] boot_service(u54_2) :: [Error] -> [Idle]
[218.699804] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[218.724533] boot_service(u54_3) :: [Error] -> [Idle]
[218.731312] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[218.756041] boot_service(u54_4) :: [Error] -> [Idle]
[218.762820] loop 19363893 took 75620163 ticks (max 75620163 ticks)
[225.525938] loop 20000000 took 4735 ticks (max 75620163 ticks)
[246.152248] Watchdog has triggered - 10
[246.157855] Boot image passed CRC
[246.162820] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[246.170146] Boot image passed CRC
[246.175111] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[246.182437] Boot image passed CRC
[246.187402] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[246.194728] Boot image passed CRC
[246.199693] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[246.206949] boot_service(u54_1) :: [Init] -> [SetupPMP]
[246.214015] boot_service(u54_2) :: [Init] -> [SetupPMP]
[246.221080] boot_service(u54_3) :: [Init] -> [SetupPMP]
[246.228146] boot_service(u54_4) :: [Init] -> [SetupPMP]
[246.235211] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[246.244473] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[246.252684] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[246.260896] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[246.269107] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[247.206859] boot_service(u54_1)::Timeout after 81441 iterations
[247.214689] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[247.222614] boot_service(u54_2)::Timeout after 81441 iterations
[247.230443] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[247.238368] boot_service(u54_3)::Timeout after 81441 iterations
[247.246197] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[247.254122] boot_service(u54_4)::Timeout after 81441 iterations
[247.261951] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[247.269876] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[247.294605] boot_service(u54_1) :: [Error] -> [Idle]
[247.301385] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[247.326114] boot_service(u54_2) :: [Error] -> [Idle]
[247.332893] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[247.357622] boot_service(u54_3) :: [Error] -> [Idle]
[247.364401] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[247.389131] boot_service(u54_4) :: [Error] -> [Idle]
[252.474213] loop 22500000 took 4741 ticks (max 75620163 ticks)
[274.785337] Watchdog has triggered - 10
[274.790944] Boot image passed CRC
[274.795909] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[274.803235] Boot image passed CRC
[274.808200] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[274.815526] Boot image passed CRC
[274.820491] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[274.827817] Boot image passed CRC
[274.832782] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[274.840039] boot_service(u54_1) :: [Init] -> [SetupPMP]
[274.847104] boot_service(u54_2) :: [Init] -> [SetupPMP]
[274.854170] boot_service(u54_3) :: [Init] -> [SetupPMP]
[274.861235] boot_service(u54_4) :: [Init] -> [SetupPMP]
[274.868301] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[274.877562] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[274.885773] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[274.893985] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[274.902196] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[275.839949] boot_service(u54_1)::Timeout after 81695 iterations
[275.847778] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[275.855703] boot_service(u54_2)::Timeout after 81695 iterations
[275.863532] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[275.871457] boot_service(u54_3)::Timeout after 81695 iterations
[275.879286] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[275.887211] boot_service(u54_4)::Timeout after 81695 iterations
[275.895041] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[275.902965] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[275.927695] boot_service(u54_1) :: [Error] -> [Idle]
[275.934474] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[275.959203] boot_service(u54_2) :: [Error] -> [Idle]
[275.965982] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[275.990711] boot_service(u54_3) :: [Error] -> [Idle]
[275.997491] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[276.22220] boot_service(u54_4) :: [Error] -> [Idle]
[279.579657] loop 25000000 took 4747 ticks (max 75620163 ticks)
[303.418426] Watchdog has triggered - 10
[303.424034] Boot image passed CRC
[303.428999] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[303.436325] Boot image passed CRC
[303.441290] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[303.448616] Boot image passed CRC
[303.453581] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[303.460906] Boot image passed CRC
[303.465871] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[303.473128] boot_service(u54_1) :: [Init] -> [SetupPMP]
[303.480193] boot_service(u54_2) :: [Init] -> [SetupPMP]
[303.487259] boot_service(u54_3) :: [Init] -> [SetupPMP]
[303.494324] boot_service(u54_4) :: [Init] -> [SetupPMP]
[303.501390] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[303.510651] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[303.518863] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[303.527074] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[303.535285] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[304.473047] boot_service(u54_1)::Timeout after 81402 iterations
[304.480876] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[304.488801] boot_service(u54_2)::Timeout after 81402 iterations
[304.496630] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[304.504555] boot_service(u54_3)::Timeout after 81402 iterations
[304.512384] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[304.520309] boot_service(u54_4)::Timeout after 81402 iterations
[304.528138] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[304.536732] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[304.561461] boot_service(u54_1) :: [Error] -> [Idle]
[304.568240] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[304.592969] boot_service(u54_2) :: [Error] -> [Idle]
[304.599748] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[304.624478] boot_service(u54_3) :: [Error] -> [Idle]
[304.631257] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[304.655986] boot_service(u54_4) :: [Error] -> [Idle]
[306.642890] loop 27500000 took 4729 ticks (max 75620163 ticks)
[332.51516] Watchdog has triggered - 10
[332.57027] Boot image passed CRC
[332.61897] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[332.69127] Boot image passed CRC
[332.73997] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[332.81227] Boot image passed CRC
[332.86097] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[332.93327] Boot image passed CRC
[332.98197] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[332.105358] boot_service(u54_1) :: [Init] -> [SetupPMP]
[332.112423] boot_service(u54_2) :: [Init] -> [SetupPMP]
[332.119489] boot_service(u54_3) :: [Init] -> [SetupPMP]
[332.126554] boot_service(u54_4) :: [Init] -> [SetupPMP]
[332.133620] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[332.142881] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[332.151093] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[332.159304] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[332.167515] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[333.105268] boot_service(u54_1)::Timeout after 80404 iterations
[333.113097] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[333.121022] boot_service(u54_2)::Timeout after 80404 iterations
[333.128851] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[333.136776] boot_service(u54_3)::Timeout after 80404 iterations
[333.144606] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[333.152530] boot_service(u54_4)::Timeout after 80404 iterations
[333.160360] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[333.168285] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[333.193014] boot_service(u54_1) :: [Error] -> [Idle]
[333.199793] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[333.224522] boot_service(u54_2) :: [Error] -> [Idle]
[333.231301] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[333.256031] boot_service(u54_3) :: [Error] -> [Idle]
[333.262810] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[333.287539] boot_service(u54_4) :: [Error] -> [Idle]
[333.740948] loop 30000000 took 4767 ticks (max 75620163 ticks)
[360.383209] loop 32500000 took 4767 ticks (max 75620163 ticks)
[360.684605] Watchdog has triggered - 10
[360.690212] Boot image passed CRC
[360.695177] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[360.702503] Boot image passed CRC
[360.707468] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[360.714794] Boot image passed CRC
[360.719759] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[360.727085] Boot image passed CRC
[360.732050] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[360.739306] boot_service(u54_1) :: [Init] -> [SetupPMP]
[360.746372] boot_service(u54_2) :: [Init] -> [SetupPMP]
[360.753437] boot_service(u54_3) :: [Init] -> [SetupPMP]
[360.760503] boot_service(u54_4) :: [Init] -> [SetupPMP]
[360.767568] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[360.776830] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[360.785041] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[360.793253] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[360.801464] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[361.739216] boot_service(u54_1)::Timeout after 81212 iterations
[361.747046] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[361.754971] boot_service(u54_2)::Timeout after 81212 iterations
[361.762800] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[361.770725] boot_service(u54_3)::Timeout after 81212 iterations
[361.778554] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[361.786479] boot_service(u54_4)::Timeout after 81212 iterations
[361.794308] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[361.802233] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[361.826962] boot_service(u54_1) :: [Error] -> [Idle]
[361.833741] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[361.858471] boot_service(u54_2) :: [Error] -> [Idle]
[361.865250] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[361.889979] boot_service(u54_3) :: [Error] -> [Idle]
[361.896758] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[361.921488] boot_service(u54_4) :: [Error] -> [Idle]
[387.345850] loop 35000000 took 4730 ticks (max 75620163 ticks)
[389.317694] Watchdog has triggered - 10
[389.323301] Boot image passed CRC
[389.328266] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[389.335592] Boot image passed CRC
[389.340557] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[389.347883] Boot image passed CRC
[389.352848] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[389.360174] Boot image passed CRC
[389.365139] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[389.372396] boot_service(u54_1) :: [Init] -> [SetupPMP]
[389.379461] boot_service(u54_2) :: [Init] -> [SetupPMP]
[389.386527] boot_service(u54_3) :: [Init] -> [SetupPMP]
[389.393592] boot_service(u54_4) :: [Init] -> [SetupPMP]
[389.400658] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[389.409919] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[389.418130] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[389.426342] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[389.434553] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[390.372306] boot_service(u54_1)::Timeout after 81403 iterations
[390.380135] boot_service(u54_1) :: [SetupPMPComplete] -> [Error]
[390.388060] boot_service(u54_2)::Timeout after 81403 iterations
[390.395889] boot_service(u54_2) :: [SetupPMPComplete] -> [Error]
[390.403814] boot_service(u54_3)::Timeout after 81403 iterations
[390.411643] boot_service(u54_3) :: [SetupPMPComplete] -> [Error]
[390.419568] boot_service(u54_4)::Timeout after 81403 iterations
[390.427398] boot_service(u54_4) :: [SetupPMPComplete] -> [Error]
[390.435322] boot_service(u54_1)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[390.460052] boot_service(u54_1) :: [Error] -> [Idle]
[390.466831] boot_service(u54_2)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[390.491560] boot_service(u54_2) :: [Error] -> [Idle]
[390.498339] boot_service(u54_3)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[390.523069] boot_service(u54_3) :: [Error] -> [Idle]
[390.529848] boot_service(u54_4)::
*******************************************************************
* WARNING: Boot Error - transitioning to IDLE *
*******************************************************************
[390.554577] boot_service(u54_4) :: [Error] -> [Idle]
[414.387409] loop 37500000 took 4754 ticks (max 75620163 ticks)
[417.950783] Watchdog has triggered - 10
[417.956391] Boot image passed CRC
[417.961356] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[417.968682] Boot image passed CRC
[417.973647] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[417.980972] Boot image passed CRC
[417.985937] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[417.993263] Boot image passed CRC
[417.998228] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[418.05485] boot_service(u54_1) :: [Init] -> [SetupPMP]
[418.12455] boot_service(u54_2) :: [Init] -> [SetupPMP]
[418.19425] boot_service(u54_3) :: [Init] -> [SetupPMP]
[418.26395] boot_service(u54_4) :: [Init] -> [SetupPMP]
[418.33365] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[418.42531] No space in queue!!!!!!
[418.47591] u54_1: failed to send message, so freeing
[418.54084] No space in queue!!!!!!
[418.59145] u54_2: failed to send message, so freeing
[418.65637] No space in queue!!!!!!
[418.70698] u54_3: failed to send message, so freeing
[418.77190] No space in queue!!!!!!
[418.82251] u54_4: failed to send message, so freeing
[418.88743] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[418.96859] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[418.104975] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[418.113186] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
[419.05395] boot_service(u54_1)::Timeout after 78463 iterations
[419.13129] modules/ssmb/ipi/ssmb_ipi.c:626: IPI_MessageFree() Assertion failed:
IPI_DATA.ipi_completes[index].used
^^^ SYSTEM REBOOTS NOW ^^^
HSS: decompressing from eNVM to L2 Scratch ... Passed
DDR training ... Passed ( 5217 ms)
[6.166229] PolarFire(R) SoC Hart Software Services (HSS) - version 0.99.33-dev-build
MPFS HAL version 2.0.101 / DDR Driver version 0.4.018 / Mi-V IHC version 0.1.1 / BOARD=mpfs-icicle-kit-es
(c) Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions.
incorporating OpenSBI - version 1.0
(c) Copyright 2019-2022 Western Digital Corporation.
[6.201747] Build ID: c1ed11d489121cad7a3dcd5f528cd463e22c402e
[6.209290] Built with the following tools:
- riscv64-unknown-elf-gcc (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0
- GNU ld (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 2.32
[6.233351] NOTICE: Running from L2 Scratchpad
[6.239557] Serial Number:
5995625459b1187379e72b44fa110c2100000000000000000000000000000000000000000000000000000000000000000000
[6.253498] Segment Configuration:
Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000
Cached: SEG0_1: offset 0x1000000000, physical DDR 0x02000000
Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x78000000
Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x78000000
[6.285101] L2 Cache Configuration:
L2-Scratchpad: 4 ways (512 KiB)
L2-Cache: 8 ways (1024 KiB)
L2-LIM: 4 ways (512 KiB)
[6.301047] DDR-Lo size is 32 MiB
[6.305725] DDR-Hi size is 1888 MiB
[6.310404] Please ensure that jumpers J34/J43 are correct for 1.8V MMC voltage...
[6.319952] Attempting to select SDCARD ... Passed
Press a key to enter CLI, ESC to skip
Timeout in 1 second
..
[7.357385] CLI boot interrupt timeout
[7.362350] Initializing Mi-V IHC
[7.366838] Initializing IPI Queues (6056 bytes @ 0xa02cf20)...
[7.374190] Initializing PMPs
[7.378295] Initializing Boot Image ...
[7.383356] Trying to boot via MMC ...
[7.388321] Preparing to copy from MMC to DDR ...
[7.396228] Validated GPT Header ...
[7.426938] Validated GPT Partition Entries ...
[7.433049] Boot Partition found at index 1
[7.438569] Attempting to read image header (1632 bytes) ...
[7.447848] Copying 691440 bytes to 0xa0000000
[7.482533] MMC: Boot Image registered ...
[7.487950] Boot image passed CRC
[7.492724] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
[7.499789] wdog_service monitoring U54_1 U54_2 U54_3 U54_4
[7.506759] ipi_poll_service :: [Init] -> [Monitoring]
[7.513538] boot_service(u54_1) :: [Init] -> [SetupPMP]
[7.520413] boot_service(u54_2) :: [Init] -> [SetupPMP]
[7.527288] boot_service(u54_3) :: [Init] -> [SetupPMP]
[7.534162] boot_service(u54_4) :: [Init] -> [SetupPMP]
[7.541037] usbdmsc_service :: [Init] -> [Idle]
[7.547147] scrub_service :: [init] -> [scrubbing]
[7.553544] beu_service :: [init] -> [monitoring]
[7.559846] u54 State Change: [Idle] [Idle] [Idle] [Idle]
[7.568057] loop 1 took 31852033 ticks (max 31852033 ticks)
[7.575314] boot_service(u54_1)::Registering domain "u-boot.bin" (hart mask 0x1e)
[7.584385] boot_service(u54_1) :: [SetupPMP] -> [SetupPMPComplete]
[7.592405] boot_service(u54_2) :: [SetupPMP] -> [SetupPMPComplete]
[7.600425] boot_service(u54_3) :: [SetupPMP] -> [SetupPMPComplete]
[7.608445] boot_service(u54_4) :: [SetupPMP] -> [SetupPMPComplete]
>> [7.616804] u54 State Change: [Booting] [Booting] [Booting] [Booting]
[7.626161] boot_service(u54_1) :: [SetupPMPComplete] -> [ZeroInit]
[7.634182] boot_service(u54_2) :: [SetupPMPComplete] -> [ZeroInit]
[7.642202] boot_service(u54_3) :: [SetupPMPComplete] -> [ZeroInit]
[7.650222] boot_service(u54_4) :: [SetupPMPComplete] -> [ZeroInit]
[7.658243] boot_service(u54_1) :: [ZeroInit] -> [Download]
[7.665499] boot_service(u54_2) :: [ZeroInit] -> [Download]
[7.672756] boot_service(u54_3) :: [ZeroInit] -> [Download]
[7.680012] boot_service(u54_4) :: [ZeroInit] -> [Download]
[7.687269] boot_service(u54_1)::Processing boot image: "u-boot.bin"
[7.695098] boot_service(u54_2) :: [Download] -> [Idle]
[7.701973] boot_service(u54_3) :: [Download] -> [Idle]
[7.708847] boot_service(u54_4) :: [Download] -> [Idle]
[7.764382] boot_service(u54_1) :: [Download] -> [OpenSBIInit]
[7.771925] boot_service(u54_1)::u54_2:sbi_init 0x1000200000
[7.778990] boot_service(u54_1)::u54_3:sbi_init 0x1000200000
[7.786056] boot_service(u54_1)::u54_4:sbi_init 0x1000200000
[7.793121] boot_service(u54_1) :: [OpenSBIInit] -> [Wait]
[7.800282] boot_service(u54_1)::u54_1:sbi_init 0x1000200000
[7.808684] boot_service(u54_1)::Checking for IPI ACKs: - -
[7.863967] boot_service(u54_1)::Checking for IPI ACKs: ACK/IDLE ACK
[7.892516] boot_service(u54_1) :: [Wait] -> [Idle]
[7.910275] u54 State Change: [SBIHartInit] [Booting] [Booting] [Booting]
[7.944839] loop 2706 took 64506354 ticks (max 64506354 ticks)
[8.45570] u54 State Change: [Running] [SBIWaitForColdboot] [SBIWaitForColdboot] [SBIWaitForColdboot]
[12.823494] u54 State Change: [Running] [Running] [Running] [Running]
[37.478383] loop 2500000 took 4732 ticks (max 64506354 ticks)
Sorry if this is not a bug, just maybe a misconfiguration.
My use case is to run the Keystone Enclave on the PolarFire SoC, for
this, I need a custom OpenSBI as security monitor.
I builded the OpenSBI firmware with the U-Boot as payload.
In principle everything works fine but during the boot process the Linux kernel
can't access the other cores. I have the same problem when using the vanilla
OpenSBI firmware.
Do I need to change anything in the default HSS config if I want to use my own
OpenSBI?
After following training #4 from :
https://www.microchip.com/training/webinars/fpgas/risc-v-innovation-unleashed-training-series/risc-v-innovation-unleashed-training-archive
I followed the steps up to making the build but I am having the followin error:
"
16:09:57 **** Incremental Build of configuration Default for project hart-software-services ****
env MSYSTEM=MSYS2 "PATH=/bin:/usr/bin:/usr/local/bin:/home//.local/bin:C:\Microchip\SoftConsole-v6.6\/riscv-unknown-elf-gcc/bin" BOARD=mpfs-icicle-kit-es make all
Cannot run program "env": Launching failed
Error: Program "env" not found in PATH
"
Is the gitlab out of synch with softconsole?
Also I tried to compile it via linux but get into trouble with the cross compiler riscv64-linux-gcc, I did not find which file to source to setup the environment variables. Or do I need to set them manually?
make: *** No rule to make target 'baremetal/drivers/mss_envm/mss_envm.c', needed by 'baremetal/drivers/mss_envm/mss_envm.o'. Stop.
hart-software-services / boards / mpfs-icicle-kit-es / Makefile
EXTRA_SRCS-$(CONFIG_SERVICE_YMODEM) += baremetal/drivers/mss_envm/mss_envm.c
"baremetal/drivers/mss_envm" not found:
https://github.com/polarfire-soc/hart-software-services/tree/master/baremetal/drivers
Could you please release baremetal/drivers/mss_envm for PMP demo, please ?
Best Regards,
The SoftConsole Python path, since at least SoftConsole v2021.1, is:
$SC_INSTALL_DIR/python3
The build instructions specify incorrect paths.
$ export PATH=$PATH:$SC_INSTALL_DIR/python/bin:$SC_INSTALL_DIR/riscv-unknown-elf-gcc/bin
C:\> path %SystemRoot%;%SC_INSTALL_DIR%\build_tools\bin;%SC_INSTALL_DIR%\python3;%SC_INSTALL_DIR%\python;%SC_INSTALL_DIR%\riscv-unknown-elf-gcc\bin
Also - %SystemRoot%
in the Windows should probably be %PATH%
?
And/or %PATH%
should be put at the end of the modified PATH
?
when I try to build hss by instruction of MainPage compiler return an error:
INFO: Linux detected
mpfs-icicle-kit-es selected
INFO: Not enabling -flto as stack protector enabled
INFO: Expected riscv64-unknown-elf-gcc version 8.3.0 but found 9.3.0
GENCONFIG
CC application/hart0/hss_state_machine.o
In file included from application/hart0/hss_state_machine.c:22:
./include/hss_debug.h:44:14: fatal error: inttypes.h: No such file or directory
44 | # include "inttypes.h"
| ^~~~~~~~~~~~
compilation terminated.
make: *** [envm-wrapper/Makefile:52: application/hart0/hss_state_machine.o] Error
How can I fix it ...,
Hi,
We are currently using latest HSS (0.99.33, release 2022.10) together with SoftConsole 2022.2 on an IcicleKit.
When programmed in Non Secure Boot Mode 1 (via SoftConsole), HSS boots successfully and proceeds with the load of u-boot then our Linux image.
When programming the same HSS binary in Factory Secure Boot Mode 3 (still through SoftConsole), HSS hangs at the Memory testing stage (as logs show below).
The root cause does not seem to be the DDR testing itself though, as disabling CONFIG_MEMTEST just leads the HSS to hang at a later stage. It's more looking like a memory mapping issue.
Any idea what is going on ?
Some additional notes:
HSS Boot log in Non-Secure Boot Mode 1 (succeeds):
[6.238558] PolarFire(R) SoC Hart Software Services (HSS) - version 0.99.33-dev-build
MPFS HAL version 2.0.101 / DDR Driver version 0.4.018 / Mi-V IHC version 0.1.1 / BOARD=mpfs-icicle-kit-es
(c) Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions.
incorporating OpenSBI - version 1.0
(c) Copyright 2019-2022 Western Digital Corporation.
[6.274077] Build ID: 60f067913789680ee6a23d010d5d0c0629633be4
[6.281620] Built with the following tools:
- riscv64-unknown-elf-gcc (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0
- GNU ld (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 2.32
[6.305680] NOTICE: Running from L2 Scratchpad
[6.311887] Serial Number:
5995625459b1187379e72b44fa110c2100000000000000000000000000000000000000000000000000000000000000000000
[6.325827] Segment Configuration:
Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000
Cached: SEG0_1: offset 0x1000000000, physical DDR 0x02000000
Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x78000000
Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x78000000
[6.357431] L2 Cache Configuration:
L2-Scratchpad: 4 ways (512 KiB)
L2-Cache: 8 ways (1024 KiB)
L2-LIM: 4 ways (512 KiB)
[6.373376] DDR-Lo size is 32 MiB
[6.378054] DDR-Hi size is 1888 MiB
[6.382733] Please ensure that jumpers J34/J43 are correct for 1.8V MMC voltage...
[6.392281] Attempting to select SDCARD ... Failed
[6.450341] Attempting to select eMMC ... Passed
Press a key to enter CLI, ESC to skip
Timeout in 1 second
..
[7.803883] CLI boot interrupt timeout
[7.808848] Initializing Mi-V IHC
[7.813336] Initializing IPI Queues (6056 bytes @ 0xa02cf20)...
[7.820688] Initializing PMPs
[7.824793] Initializing Boot Image ...
[7.829854] Trying to boot via MMC ...
[7.834819] Preparing to copy from MMC to DDR ...
[7.841711] Validated GPT Header ...
[7.863107] Validated GPT Partition Entries ...
[7.869079] Boot Partition found at index 1
[7.874556] Attempting to read image header (1632 bytes) ...
[7.884251] Copying 691440 bytes to 0xa0000000
[7.898790] MMC: Boot Image registered ...
[7.904207] Boot image passed CRC
[7.908981] Boot image set name: "PolarFire-SoC-HSS::U-Boot"
<<< boot continues >>>
HSS Boot log in Factory-Secure Boot Mode 3 (fails):
[6.237898] PolarFire(R) SoC Hart Software Services (HSS) - version 0.99.33-dev-build
MPFS HAL version 2.0.101 / DDR Driver version 0.4.018 / Mi-V IHC version 0.1.1 / BOARD=mpfs-icicle-kit-es
(c) Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions.
incorporating OpenSBI - version 1.0
(c) Copyright 2019-2022 Western Digital Corporation.
[6.273416] Build ID: 60f067913789680ee6a23d010d5d0c0629633be4
[6.280959] Built with the following tools:
- riscv64-unknown-elf-gcc (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0
- GNU ld (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 2.32
[6.305020] NOTICE: Running from L2 Scratchpad
[6.311226] Serial Number:
5995625459b1187379e72b44fa110c2100000000000000000000000000000000000000000000000000000000000000000000
[6.325166] Segment Configuration:
Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000
Cached: SEG0_1: offset 0x1000000000, physical DDR 0x02000000
Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x78000000
Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x78000000
[6.356770] L2 Cache Configuration:
L2-Scratchpad: 4 ways (512 KiB)
L2-Cache: 8 ways (1024 KiB)
L2-LIM: 4 ways (512 KiB)
[6.372715] DDR-Lo size is 0 MiB
<<< HSS hangs here >>>
mpfsBootmodeProgrammer boot log (for boot mode 3):
18:01:04 DEBUG - Looking for ELF file in the work directory.
18:01:04 DEBUG - ELF file found: "hss-envm-wrapper.elf".
18:01:04 INFO - Selected boot mode "3 - factory secure boot from eNVM" and working in directory "c:\Microchip\hart-software-services\Default".
18:01:04 DEBUG - Workdir=c:\Microchip\hart-software-services\Default die=MPFS250T_ES diePackage=FCVG484 bm=3 - factory secure boot from eNVM verify=true elf=hss-envm-wrapper.elf
18:01:04 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe new_project --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject --target_die MPFS250T_ES --target_package FCVG484".
18:01:04 DEBUG - Finished with exit code: "0".
18:01:04 INFO - Generating BIN file...
18:01:04 DEBUG - Invoking command: "C:\Microchip\SoftConsole-v2022.2\/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-objcopy.exe --version".
18:01:04 DEBUG - Finished with exit code: "0".
18:01:04 DEBUG - Invoking command: "C:\Microchip\SoftConsole-v2022.2\/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-objcopy.exe -O binary c:\Microchip\hart-software-services\Default/hss-envm-wrapper.elf c:\Microchip\hart-software-services\Default/bootmode3/hss-envm-wrapper.bin ".
18:01:04 DEBUG - Finished with exit code: "0".
18:01:04 DEBUG - Size of the BIN file is "95184 (decimal)" or "0x000173D0 (hex)".
18:01:04 DEBUG - Invoking command: "C:\Microchip\SoftConsole-v2022.2\/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-readelf.exe --program-headers c:\Microchip\hart-software-services\Default/hss-envm-wrapper.elf ".
18:01:05 DEBUG - Finished with exit code: "0".
18:01:05 DEBUG - Entry point 0x20220100
18:01:05 DEBUG - The detected entry address is "20220100".
18:01:05 INFO - Generating SBIC (Secure Boot Image Certificate)...
18:01:05 INFO - Generating ECDSA NIST P-384 keys...
18:01:05 DEBUG - Public key X(hex)=0x36a32b90aed78a26fef24130e019dfbb819bb43a1d93446977fbc41a585996ca7fbfbbb917a90600db941a687a4c26b5
18:01:05 DEBUG - Public key Y(hex)=0xebcdbbfea25d1c2973492ff97a02bf59446229218d6ea8287dbe656073e3ada5b85fcedf968430a551da3509bc1d21bb
18:01:05 INFO - Generating HEX file...
18:01:05 DEBUG - Invoking command: "C:\Microchip\SoftConsole-v2022.2\/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-objcopy.exe -I binary -O ihex --change-section-lma *+0x20220000 c:\Microchip\hart-software-services\Default/bootmode3/hss-envm-wrapper-bm3-p0.bin c:\Microchip\hart-software-services\Default/bootmode3/hss-envm-wrapper-bm3-p0.hex ".
18:01:05 DEBUG - Finished with exit code: "0".
18:01:05 INFO - Preparing for bitstream generation...
18:01:05 DEBUG - Getting the SBIC address page '(BootVector(0x20220100) / 256) - 1 = 0x00000000'.
18:01:05 DEBUG - Getting the SBIC address 'SbicPage(0x00000000) * 256 = 0x20220000'.
18:01:05 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe mss_boot_info --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject --u_mss_bootmode 3 --u_mss_bootcfg 0000000000000000000000000000000020220000 --ucskx 36a32b90aed78a26fef24130e019dfbb819bb43a1d93446977fbc41a585996ca7fbfbbb917a90600db941a687a4c26b5 --ucsky ebcdbbfea25d1c2973492ff97a02bf59446229218d6ea8287dbe656073e3ada5b85fcedf968430a551da3509bc1d21bb --reset_sbic_version".
18:01:05 DEBUG - Finished with exit code: "0".
18:01:05 DEBUG - Getting the SBIC address page '(BootVector(0x20220100) / 256) - 1 = 0x00000000'.
18:01:05 DEBUG - Getting the SBIC address 'SbicPage(0x00000000) * 256 = 0x20220000'.
18:01:05 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe envm_client --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject --number_of_bytes 95440 --content_file_format intel-hex --content_file c:\Microchip\hart-software-services\Default/bootmode3/hss-envm-wrapper-bm3-p0.hex --start_page 0 --client_name bootmode3_0 --mem_file_base_address 20220000".
18:01:06 DEBUG - Finished with exit code: "0".
18:01:06 INFO - Generating bitstream...
18:01:06 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe generate_bitstream --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject".
18:01:21 DEBUG - Finished with exit code: "0".
18:01:21 INFO - Programming the target...
18:01:21 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe run_action --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject --action PROGRAM".
18:01:31 DEBUG - Finished with exit code: "0".
18:01:31 INFO - Verifying the target...
18:01:31 DEBUG - Invoking command: "C:/Microchip/Libero_SoC_v2022.2/Designer/bin64//fpgenprog.exe run_action --location c:\Microchip\hart-software-services\Default/bootmode3/fpgenprogProject --action VERIFY".
18:01:38 DEBUG - Finished with exit code: "0".
18:01:38 INFO - mpfsBootmodeProgrammer completed successfully.
Thanks for your inputs.
Hi!
I am trying to understand how to use the mss_envm driver which I found shipped with the HSS here: https://github.com/polarfire-soc/hart-software-services/tree/master/baremetal/drivers/mss_envm
According to my understanding, we should fill with a buffer envm_set_page_data()
and then load the buffer into envm with this function: envm_program_page_address()However, in order to initialize the driver, we need to call envm_init()
. This function takes as parameter p_envm_params. Which system service it is needed to call to fill this variable?The function which needs to be called after instead is envm_set_clock()
, which is taking as input mss_frequency, but what is mss_frequency? Is LIBERO_SETTING_MSS_SYSTEM_CLK ?Can you provide an example of how to use this driver?? Also, it is possible to use it to change some values written in the eNVM at runtime?
Thanks!!!
Use the pre-built toolchain from
https://toolchains.bootlin.com/downloads/releases/toolchains/riscv64/tarballs/riscv64--glibc--bleeding-edge-2020.08-1.tar.bz2
On the following HSS commit: (HEAD as of now)
commit 58b03943834fe34991dc5fa924436b3620e07aa5 (HEAD -> master, origin/master, origin/HEAD)
Merge: 7383f7e c3341b9
Author: Cyril-Jean <[email protected]>
Date: Tue Jan 19 10:43:27 2021 +0000
Merge pull request #10 from kraj/master
hss-payload-generator: Rename EM_ARC_COMPACT2 to EM_ARCV2
$ export CROSS_COMPILE=riscv64-linux-
$ cp boards/mpfs-icicle-kit-es/def_config .config
$ make BOARD=mpfs-icicle-kit-es
riscv64-buildroot-linux-gnu/bin/ld: Default/hss.elf section `.text' will not fit in region `envm'
riscv64-buildroot-linux-gnu/bin/ld: region `envm' overflowed by 9792 bytes
collect2: error: ld returned 1 exit status
make: *** [Makefile:177: hss.elf] Error 1
@Cyril-Jean HSS v2021.08 release notes: "Icicle Kit Reference Design Programming File" section:
should "2021.04 Icicle Kit Reference Design" be "2021.08 Icicle Kit Reference Design"?
Hello Everyone,
i found out that the default configuration of the HSS sets the clock for each hart to 125 MHz. If I want increase this value (the manual says the maximum is 625 MHz), can I write to the clk register (I did not find the correct address yet) within my own application or do I have to update the HSS and change the LIBERO_SETTING_MSS_RTC_TOGGLE_CLK constant from within Libero? Also, why is the low MHz value of 125 the default if the board is capable of 625 MHz?
Maybe I understand something completely wrong. If so, than I am sorry.
Please complete this checklist before filing an issue:
Please make sure to add all the information needed to understand the bug so that someone can help. If the info is missing we'll add the 'Needs more information' label and close the issue until there is enough information.
Refer: https://github.com/orgs/polarfire-soc/discussions/100#discussion-4167312
To Reproduce : pick latest hss and build as per above mentioned link.
D:\PFSOC\WORKSPACE\hart-software-services/init/hss_boot_init.c:421: undefined reference to 'HSS_Register_Boot_Image'
it seems I have to disable CONFIG_SERVICE_MMC too if i do that
CC build/init/hss_boot_init.o
init/hss_boot_init.c:159:6: error: #error Unable to determine boot mechanism
error Unable to determine boot mechanism
^~~~~
init/hss_boot_init.c: In function 'HSS_BootListStorageProviders':
init/hss_boot_init.c:176:28: error: comparison is always false due to limited range of data type [-Werror=type-limits]
for (uint32_t i = 0; i < ARRAY_SIZE(pStorages); i++) {
^
cc1.exe: all warnings being treated as errors
make: *** [application/rules.mk:184: build/init/hss_boot_init.o] Error 1
"make all" terminated with exit code 2. Build might be incomplete.
Since i don't need this part of the code i commented these line
Now,
<artificial>:(.rodata.globalInitFunctions+0x38): undefined reference to 'HSS_PMP_Init'
in hss_registry.c HSS_PMP_Init is referenced without checking IS_ENABLED(IS_ENABLED(CONFIG_SERVICE_BOOT))
With these changes I am able to build and debug the HSS, But I am not sure what are the other parts are actually affected.
So it needs a further lookup and proper fix.
Hi,
We are currently facing an issue transitioning from a DEV workflow to a PROD workflow.
We have previously validated that we could program the HSS in Secure Boot Mode 3 using either LiberoSoC or SoftConsole (via mpfsBootmodeProgrammer) on a IcicleKit board with NO security settings applied.
For PROD use, we now have our boards protected by UPK1/2 and UEK1/2 keys.
The idea here is that the fabric is programmed using UEK1 first, and the eNVM/sNVM is programmed using UEK2 later on (at a separate facility).
What we observe is that:
Could it be that this scenario is not supported ?
Thanks in advance for your help !
NB: SW Versions are LiberoSoC 2022.3 (also tried 2023.1), HSS 2022.2, SoftConsole 2022.2
With the latest hart-software-services as of today (commit: 58b0394), the sdcard detection hangs always:
[1.939392] HSS_MMCInit(): Attempting to select SDCARD ... ▒▒▒
Commenting this line below will no longer cause the board to hang:
HW_set_uint32(SDIO_REGISTER_ADDRESS, 1);
but the sdcard never works. I've tried 3.3v/1.8v dip switch, different releases, no matter what, the system gets an error at MSS_MMC_init() function, on line 657. I'm using the board mpfs-icicle-kit-es and Microchip SoftConsole v6.5.0.442.
Ciao!
This is just to report that, current version of HSS fails to boot on MPFS250T_ES die FCSG536 package. The issue seems to be somewhere into the HAL code.
From my tests, something in the mss_nwc_init() causes the CPU to reset. To get it working, I had to update the mpfs_hal to the latest version available from the platform repo.
Do you plan to update BsP version shipped with HSS ? Thanks
#2 addressed the build failure of HSS when built with GCC 10.1.0
However the HSS image built by GCC 10.1.0 does not boot. Changing compiler back to GCC 9.2.0, the image boots again.
The export $PATH command explaining how to use make properly does not point to the proper cross compiler. In my case, I renamed the directory to match the directory to the path. This broke the ability to run SoftConsole. This might be more effort, but could the export $PATH instruction have the actual directory name going forward?
Makes it a bit easier for us learning how to develop for PolarFire.
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