• In 2022, the second semester of the third grade

1. lab1

• Design the 1-bit Full Adder as Verilog and verify with simulation.

• 4-bit 4:1 Mux design with enable signal

2. lab2

• Design three 32-bit Adder.

  • Carry Ripple Adder

  • Carry Lookahead Adder

  • One of Brent Kung Adder, Sklansky Adder, Kogge Stone Adder

• Apply pipelines to the adders presented above, respectively.

3. lab3

• Bit width configurable 8-bit array multiplier code creation.

• Apply pipelines to code written above.

4. lab4_front-end

• Synthesis & Optimization with BW = 8, 16, 32 for Bit Width Configurable Multiplier.

5. lab5_back-end

• STA Timing Report creation

• After adding Floor Planning VDD and VSS Ring, proceed with Routing Optimization and check the Placement Color Hierarchy and CTS Latency Color

6. Final_Project

• Design and implement 16-bit floating-point multiplier and measure area/power/latency using IEEE 16-bits floating-point format