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View Code? Open in Web Editor NEWVideocore Backend for llvm
License: Other
Videocore Backend for llvm
License: Other
Low Level Virtual Machine (LLVM) ================================ This directory and its subdirectories contain source code for the Low Level Virtual Machine, a toolkit for the construction of highly optimized compilers, optimizers, and runtime environments. LLVM is open source software. You may freely distribute it under the terms of the license agreement found in LICENSE.txt. Please see the documentation provided in docs/ for further assistance with LLVM, and in particular docs/GettingStarted.rst for getting started with LLVM and docs/README.txt for an overview of LLVM's documentation setup. If you're writing a package for LLVM, see docs/Packaging.rst for our suggestions.
Operands don't show scalar register offsets and will potentially show the wrong orientation.
phire@nirrit:~/projects/llvm/build$ echo "st r0, (r3+sp)" | bin/llvm-mc -arch=videocore -show-encoding
.text
llvm-mc: /home/phire/projects/llvm/llvm32/lib/Target/Videocore/MCTargetDesc/VideocoreMCCodeEmitter.cpp:134: unsigned int {anonymous}::VideocoreMCCodeEmitter::getMachineOpValue(const llvm::MCInst&, const llvm::MCOperand&, llvm::SmallVectorImpl<llvm::MCFixup>&) const: Assertion `Kind == MCExpr::SymbolRef' failed.
0 llvm-mc 0x000000000060c21d
1 llvm-mc 0x000000000060c49a
2 llvm-mc 0x000000000060bf13
3 libpthread.so.0 0x00007fd48e807870
4 libc.so.6 0x00007fd48da50369 gsignal + 57
5 libc.so.6 0x00007fd48da51768 abort + 328
6 libc.so.6 0x00007fd48da49456
7 libc.so.6 0x00007fd48da49502
8 llvm-mc 0x00000000004cb8a2
9 llvm-mc 0x00000000004cbe15
10 llvm-mc 0x00000000004cb661
11 llvm-mc 0x000000000055ebf4
12 llvm-mc 0x000000000055f77d
13 llvm-mc 0x0000000000421633
14 llvm-mc 0x00000000005129f7
15 llvm-mc 0x000000000050ea91
16 llvm-mc 0x000000000040c455
17 llvm-mc 0x000000000040d138
18 libc.so.6 0x00007fd48da3cb05 __libc_start_main + 245
19 llvm-mc 0x000000000040b6a9
Stack dump:
0. Program arguments: bin/llvm-mc -arch=videocore -show-encoding
Aborted
It might be possible to remove duplication in the instruction formats and multiclasses by using multiple inheritance.
There is only a single scalar offset field for 48bit instructions.
The destination vector uses the z flag to specify if the scalar offset field is used.
The sources vector(s) are forced to have the same orientation as the destination and the orientation flag is used to specify if the scalar offset field is used.
I need to reverse the Videocore relocations (either from the .vll files, or the .vll loader in the blob), document them, and implement them in llvm.
Need to add checking for valid registers when adding a memoperand.
I think llvm can automatically generate this.
See section in Target.td about predicates.
Instructions should be assembled to 80 bit instructions, which will somehow get converted to a 48 bit vector later if they will fit.
This will also involve calling conventions and other stuff.
Should softfail instead.
It is currently impossible to assemble arithmetic/logic instructions with immediate operands larger than 31.
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