petrpavlu / valgrind-riscv64 Goto Github PK

Valgrind with support for the RISCV64/Linux platform.

License: GNU General Public License v2.0

Emacs Lisp 0.01% Makefile 0.62% C 94.54% C++ 1.23% Perl 0.46% Assembly 1.75% Shell 0.31% M4 0.41% JavaScript 0.39% CSS 0.01% HTML 0.01% Roff 0.01% GDB 0.05% Awk 0.01% Python 0.21%

valgrind risc-v

valgrind-riscv64's Introduction

Valgrind – RISCV64/Linux

Overview

This repository contains Valgrind with support for the RISCV64/Linux platform.

The aim of the project is to enable Valgrind for the RV64GC instruction set on the Linux operating system. Once this support is implemented and has sufficient quality, it is intended for this port to become a part of the upstream Valgrind project and to continue further development there.

For installation, please follow the generic steps how to build Valgrind in the main README file.

In case you are interested in helping with the port then the best option is to analyze remaining failing tests in the Valgrind test suite, or just try the port with your application and report any discovered bugs.

The project was presented at FOSDEM 2022.

Current state

Current focus is on functionality and correctness.

The following tables summarize the basic state as of 2022-12-04.

Enabled RV64GC instructions:

Name	Description	#Enabled/#Instrs
RV64I	Base instruction set	52/52
RV64M	Integer multiplication & division	12/13
RV64A	Atomic	22/22
RV64F	Single-precision floating-point	30/30
RV64D	Double-precision floating-point	32/32
RV64Zicsr	Control & status register	2/6
RV64Zifencei	Instruction-fetch fence	0/1
RV64C	Compressed	36/37

Test results:

Test set	#Failed/#Total
Memcheck	10/219
Nulgrind	1/140
Cachegrind	0/7
Callgrind	0/15
DHAT	0/8
DRD	4/130
Helgrind	4/55
Massif	2/37
GDBserver	2/25

License

This project is released under the terms of the GPLv2 License.

valgrind-riscv64's People

Contributors

Stargazers

Watchers

Forkers

shangyunhai xeonacid laokz mfkiwl paulfloyd rjiejie jackgittes jan9401 web-logs2 revyos fabiorafaelcoutada

valgrind-riscv64's Issues

Build warnings

Building on FreeBSD amd64 with clang13 I get

priv/guest_riscv64_helpers.c:256:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:261:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:266:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:271:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:276:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:281:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:286:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:291:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:296:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]
priv/guest_riscv64_helpers.c:301:9: warning: unused variable 'rm_RISCV' [-Wunused-variable]

Prepare for upstream?

Hi,
Amazing work!
Do we have a plan to let Valgrind upstream merge this feature?
If there are need help with real riscv64 hardware resources, please let me know.
Thanks again for your great work~

Please feel free to delegate work

I would like to help you solve issues or introduce enhancements. Feel free to work together.

Support riscv

in order to support riscv,Made what changes?

riscv vector ISA support

@paulfloyd @petrpavlu
We consider to add RVV/Vector feature in valgrind and met some issues from investigation.

RVV like ARM's SVE programming model, it's scalable/VLA, that means the vector length is agnostic.
ARM's SVE is not supported in valgrind :(

There is not any VLA vector IR to represent these vector model, it's the big issue.
Also some other common module like "register allocator" in VEX can not represent vector type which use
more than one register.
In another hand, some tool plugin like Memcheck will use data type like "Ity_V128/Ity_V256" to generate IRs, it's a big challenge

Any ideas for supporting of scalable vector model ?

Regtest fails on FreeBSD amd64

First, I get these

memcheck/tests/riscv64-linux/context_float (stdout)
memcheck/tests/riscv64-linux/context_float (stderr)
memcheck/tests/riscv64-linux/context_integer (stdout)
memcheck/tests/riscv64-linux/context_integer (stderr)
memcheck/tests/riscv64-linux/scalar      (stderr)
...
Unknown directory 'riscv64'. Please update check_headers_and_includes

I also get 2 new failures

memcheck/tests/leak-segv-jmp (stderr)

That looks like a line number change due to added RISCV64 code in the .c file and the expected needs updating.

none/tests/libvexmultiarch_test (stderr)

paulf> cat none/tests/libvexmultiarch_test*diff
--- libvexmultiarch_test.stderr.exp     2023-01-29 09:36:06.883182000 +0100
+++ libvexmultiarch_test.stderr.out     2023-01-29 10:16:07.617645000 +0100
@@ -0,0 +1 @@
+valgrind: ./libvexmultiarch_test: No such file or directory

I see that this is marked as 'disable for now'. As a quick fix you could put in the .vgtest

prereq: ! ../../test/arch_test riscv64

petrpavlu / valgrind-riscv64 Goto Github PK

valgrind-riscv64's Introduction

Valgrind – RISCV64/Linux

Overview

Current state

License

valgrind-riscv64's People

Contributors

Stargazers

Watchers

Forkers

valgrind-riscv64's Issues

Build warnings

Prepare for upstream?

Please feel free to delegate work

Support riscv

riscv vector ISA support

Regtest fails on FreeBSD amd64

Recommend Projects

React

Vue.js

Typescript

TensorFlow

Django

Laravel

D3

Recommend Topics

javascript

web

server

Machine learning

Visualization

Game

Recommend Org

Facebook

Microsoft

Google

Alibaba

D3

Tencent