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apu2-documentation's Introduction

Overview

This repository contain documentation and scripts that aim to help PC Engines apuX platform users and developers to customize firmware to their needs.

Repository structure

This repository aims to gather all debug notes and documentation related to PC Engines apu1/2/3/4/5 firmware and hardware. Structure of the repository:

  • configs - directory with kernel configs used in 3mdeb pxe-server for validation purposes
  • docs - overall directory with documents
    • docs/debug - documents containing various problems debugging notes
    • docs/images - images included in certain documents
    • docs/logs - directory containing variosu logs from debugging
    • docs/research - directory with notes from research of new features
  • ipxe - iPXE scripts, headers and configuration files used in old build system
  • scripts - BASH scripts used in the old build system

Useful documents

  • Linux issues - document describes known issues with Linux of different versions and how to work around them when it's possible.

  • CPU Boost - document briefly describes what the Core Performance Boost is and how to verify it works in BIOS and operating system.

  • Fast Boot - document describing research for Fast Boot path for apu boards. The Fast Boot was intended to restore memory configuration from non-volatile storage and reduce the boot time of the platform. You will find the issues and limitations which did not allow to implement the feature.

  • ROCA - document describing ROCA TPM vulnerablity status and verification on TPM1a module form PC Engines.

  • APU mPCIe capabilities - list of all signals and interfaces present on mPCIe connectors for apu2/3/4 boards. The document also describes possible usage of the slots.

  • Cold reset - document describing reset types for the platform.

  • Firmware flashing - document describes how to flash new firmware for apu2 board on various operating systems. Also there is a description how to safely reboot the platform after a firmware update.

  • Microcode patching - a guide how to apply a microcode patch on the firmware level by building a custom firmware image.

  • mPCIe modules - list of supported and tested WiFi and LTE modules. The document also describes issues with certain modules and possible solutions/workarounds.

  • pfSense installation guide - as in the title

  • PXELINUX configuration - documents describing possible solutions when experiencing problems with PXELINUX on apu boards.

  • Old build system procedure (deprecated) - document describing build procedure for older PC Engines firmware releases. It is deprecated, do not use unless You want to build old binaries.

  • COM2 serial console - a practical guide how to build a firmware binary with native COM2 console support. If You want to use full RS232 COM1 port for other purposes, read the document how to change the main console port.

  • TPM menu - document describes the usage of TPM configuration menu in SeaBIOS.

  • TPM pin mapping - document showing the TPM1a module pinout. It may be useful for users that would like to connect the TPM1a module to boards other than apu2.

  • VBOOT HOWTO - document describing how to build a coreboot image with vboot support and measured boot mode

  • coreboot with Tianocore payload - document describes how to build a coreboot image with Tianocore payload

  • GPIO guide - quick guide how to manipulate GPIOs from Linux sysfs

  • Order of PCI addresses - Describes how PCIe devices are being numbered on APU, and how it can be changed.

  • Runtime configuration - A guide how to change apu firmware configuration options in the BIOS setup or via OS application

You may also find many other documents out there, but we have listed only the most useful. Other are mostly developers notes which may not be that interesting.

Versioning scheme change

Since version v4.8.0.1 we changed versioning scheme skipping coreboot v4.7 release.

Why we changed versioning scheme?

In recent version coreboot community introduced tag v4.8.1 this breaks our previous versioning scheme which was v4.6.z, where z was PC Engines fork patch number. Because 3rd digit was already taken by coreboot tag this breaks our versioning scheme. As a result we start to use new versioning scheme v4.8.0.w, where w will be PC Engines fork patch number as always for each new release counted from 0.

Why we skipped coreboot 4.7?

If you take a look at coreboot tag dates:

refs/tags/4.6 Sun Apr 30 19:48:38 2017 -0600
refs/tags/4.7 Mon Jan 15 00:57:04 2018 +0000
refs/tags/4.8 Tue May 15 17:40:15 2018 +0000
refs/tags/4.8.1 Wed May 16 19:07:34 2018 +0000

After release of 4.7 we simply didn't have enough time to adjust to 4.7 before 4.8 popped up. Please note that coreboot releases are just arbitrary points in time, so trying to follow mainline in each release may make more sense, but requires decent testing.

Binary releases

All information about firmware releases (including changes, fixes and known issues) are available on the PC Engines Github site pcengines.github.io.

All the newest binaries can be found there.

Also please take a look at changelogs:

Building firmware using PC Engines firmware builder

Since releases v4.6.10 and v4.0.17 build process has been simplified. PC Engines firmware builder is a dedicated tool to build fully featured apu firmware binaries using separated docker environment. It provides users-friendly scripts that allow to build release and custom binaries. For more information and usage details please visit: pce-fw-builder.

For releases older than v4.0.17 and v4.6.10 use the procedure described in this document

Branch description

  • master - keeps track of coreboot's master branch
  • release - where all releases are merged
  • develop - where current development takes place periodically synced with coreboot master
  • rel_x.y.z.w - release branches, where:
    • x is coreboot major version
    • y is coreboot minor version
    • z is coreboot patch number
    • w is PC Engines firmware fork patch number counted from 0
  • feature_branch - sample feature branch name for workflow explanation needs

Feature/bug fix development

We are in favor of Test Driven Bug Fixing (TDBF).

  1. Create automated test that validate feature or reproduce bug - test fails at this point
  2. Pull coreboot's master branch to master
  3. Merge master to develop
  4. Create new branch feature_branch from develop
  5. Commit changes to feature_branch
  6. Run regression tests and fix bugs - test written in point 1 should pass at this point
  7. Submit PR to develop

Steps for new release

  1. Checkout new branch rel_x.y.z.w from recent commit on release
  2. Merge current develop to rel_x.y.z.w
  3. End of month we close merge window
  4. Perform automated regression testing on rel_x.y.z.w including all new tests
  5. Fix all required issues and repeat point 4 until fixed - this doesn't mean all tests pass, this mean that approved set passed
  6. If results are accepted merge it to release branch
  7. Add tag, which should trigger CI and publish binaries
  8. Merge release branch to develop

Using iPXE

This option assume that your apuX is in the same networks as your PC. Your PC in this case is used as HTTP and NFS server, which will be utilized to boot apuX over iPXE.

git clone https://github.com/3mdeb/pxe-server.git
cd pxe-server
NFS_SRV_IP=<your_ip> ./init.sh
./start.sh

Please note that you may have NFS server running on host what leads to ports conflicts.

After starting NFS and HTTP you can boot apuX. Please enable network booting using sortbootorder.

iPXE> ifconf net0
iPXE> dhcp net0
iPXE> chain http://<your_ip>:8000/menu.ipxe

Choose Debian stable netboot 4.14.y after boot login ([root:debian]) and for apu2/3/4/5 run:

flashrom -p internal -w apuX_x.y.z.rom

For apu1 flashrom command line looks like that:

flashrom -p internal -w apu1_x.y.z.rom -c MX25L1605A/MX25L1606E/MX25L1608E

A full power cycle is required after flashing. See firmware_flashing.md for a workaround when this is not possible (e.g. when upgrading remotely).

Known issues

Board mismatch

Some binaries may need boardmismatch=force flashrom option because of SMBIOS table issue we had in old releases. Please double check you flashing correct binary before forcing.

Contribute

Feel free to send pull request if you find bugs, typos or will have issues with provided procedures.

apu2-documentation's People

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apu2-documentation's Issues

build fails: cp: cannot stat 'configs/config.pcengines_apu2': No such file or directory

Thanks for providing this repository, it’s very useful!

However, I had to work around the following issue to get it building:

% ./build.sh release v4.6.9 apu2
Cloning into 'release/coreboot'...
remote: Counting objects: 16120, done
remote: Finding sources: 100% (513/513)
remote: Total 385791 (delta 50), reused 385511 (delta 50)
Receiving objects: 100% (385791/385791), 84.07 MiB | 10.78 MiB/s, done.
Resolving deltas: 100% (306032/306032), done.
Submodule 'arm-trusted-firmware' (https://review.coreboot.org/arm-trusted-firmware.git) registered for path '3rdparty/arm-trusted-firmware'
Submodule '3rdparty/blobs' (https://review.coreboot.org/blobs.git) registered for path '3rdparty/blobs'
Submodule '3rdparty/chromeec' (https://review.coreboot.org/chrome-ec.git) registered for path '3rdparty/chromeec'
Submodule 'libgfxinit' (https://review.coreboot.org/libgfxinit.git) registered for path '3rdparty/libgfxinit'
Submodule 'libhwbase' (https://review.coreboot.org/libhwbase.git) registered for path '3rdparty/libhwbase'
Submodule 'vboot' (https://review.coreboot.org/vboot.git) registered for path '3rdparty/vboot'
Submodule 'util/nvidia-cbootimage' (https://review.coreboot.org/nvidia-cbootimage.git) registered for path 'util/nvidia/cbootimage'
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/arm-trusted-firmware'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/blobs'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/chromeec'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/libgfxinit'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/libhwbase'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/vboot'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/util/nvidia/cbootimage'...
Submodule path '3rdparty/arm-trusted-firmware': checked out '693e278e308441d716f7f5116c43aa150955da31'
Submodule path '3rdparty/blobs': checked out '78a02a7f9d979fcc864638cc40084e662476095f'
Submodule path '3rdparty/chromeec': checked out '11bd4c0f4d11357ab830982d7dec164813c886dd'
Submodule path '3rdparty/libgfxinit': checked out '98a673dc57d90cc79e64c53bd02cfcc1c48ea1aa'
Submodule path '3rdparty/libhwbase': checked out '637f2a4f21ead8ccc45d5256834eb27ce72088db'
Submodule path '3rdparty/vboot': checked out '392211f0358919d510179ad399d8f056180e652e'
Submodule path 'util/nvidia/cbootimage': checked out '64045f993c2cd8989838aeaad3d22107d96d5596'
remote: Counting objects: 5266, done.
remote: Compressing objects: 100% (20/20), done.
remote: Total 5266 (delta 1582), reused 1577 (delta 1574), pack-reused 3672
Receiving objects: 100% (5266/5266), 2.42 MiB | 5.16 MiB/s, done.
Resolving deltas: 100% (3562/3562), completed with 308 local objects.
From https://github.com/pcengines/coreboot
 * [new branch]            alix_early_cbmem    -> pcengines/alix_early_cbmem
 * [new branch]            apu2-uefi-new       -> pcengines/apu2-uefi-new
 * [new branch]            apu5_s1button_ml    -> pcengines/apu5_s1button_ml
 * [new branch]            coreboot-4.0.x      -> pcengines/coreboot-4.0.x
 * [new branch]            coreboot-4.5.x      -> pcengines/coreboot-4.5.x
 * [new branch]            coreboot-4.6.x      -> pcengines/coreboot-4.6.x
 * [new branch]            coreboot-4.6.x-uefi -> pcengines/coreboot-4.6.x-uefi
 * [new branch]            coreboot-4.7.x      -> pcengines/coreboot-4.7.x
 * [new branch]            coreboot-4.7.x-uefi -> pcengines/coreboot-4.7.x-uefi
 * [new branch]            coreboot-4.7.x-wip  -> pcengines/coreboot-4.7.x-wip
 * [new branch]            develop             -> pcengines/develop
 * [new branch]            disable_lpcclk0     -> pcengines/disable_lpcclk0
 * [new branch]            iommu_support       -> pcengines/iommu_support
 * [new branch]            kmalkki-xen-fixes   -> pcengines/kmalkki-xen-fixes
 * [new branch]            master              -> pcengines/master
 * [new branch]            rel_4.8.0.1         -> pcengines/rel_4.8.0.1
 * [new branch]            rel_v4.0.18         -> pcengines/rel_v4.0.18
 * [new branch]            rel_v4.6.10         -> pcengines/rel_v4.6.10
 * [new branch]            rel_v4.6.9          -> pcengines/rel_v4.6.9
 * [new branch]            release             -> pcengines/release
 * [new branch]            rtconf              -> pcengines/rtconf
 * [new branch]            runtime_config      -> pcengines/runtime_config
 * [new branch]            v0.4.1.1-sd-debug   -> pcengines/v0.4.1.1-sd-debug
 * [new branch]            v0.4.1.1-usb-debug  -> pcengines/v0.4.1.1-usb-debug
 * [new tag]               coreboot-4.7.x      -> coreboot-4.7.x
 * [new tag]               v4.0.17             -> v4.0.17
 * [new tag]               v4.5.8              -> v4.5.8
 * [new tag]               v4.6.9              -> v4.6.9
 * [new tag]               v4.7.0              -> v4.7.0
 * [new tag]               apu2b-20160304      -> apu2b-20160304
 * [new tag]               v4.0.1              -> v4.0.1
 * [new tag]               v4.0.1.1            -> v4.0.1.1
 * [new tag]               v4.0.10             -> v4.0.10
 * [new tag]               v4.0.11             -> v4.0.11
 * [new tag]               v4.0.12             -> v4.0.12
 * [new tag]               v4.0.13             -> v4.0.13
 * [new tag]               v4.0.14             -> v4.0.14
 * [new tag]               v4.0.15             -> v4.0.15
 * [new tag]               v4.0.16             -> v4.0.16
 * [new tag]               v4.0.18-test        -> v4.0.18-test
 * [new tag]               v4.0.2              -> v4.0.2
 * [new tag]               v4.0.3              -> v4.0.3
 * [new tag]               v4.0.4              -> v4.0.4
 * [new tag]               v4.0.5              -> v4.0.5
 * [new tag]               v4.0.6              -> v4.0.6
 * [new tag]               v4.0.7              -> v4.0.7
 * [new tag]               v4.0.7.1            -> v4.0.7.1
 * [new tag]               v4.0.7.2            -> v4.0.7.2
 * [new tag]               v4.0.8              -> v4.0.8
 * [new tag]               v4.0.9              -> v4.0.9
 * [new tag]               v4.5.2              -> v4.5.2
 * [new tag]               v4.5.3              -> v4.5.3
 * [new tag]               v4.5.3.1            -> v4.5.3.1
 * [new tag]               v4.5.4              -> v4.5.4
 * [new tag]               v4.5.5              -> v4.5.5
 * [new tag]               v4.5.5.1            -> v4.5.5.1
 * [new tag]               v4.5.5.2            -> v4.5.5.2
 * [new tag]               v4.5.6              -> v4.5.6
 * [new tag]               v4.5.7              -> v4.5.7
 * [new tag]               v4.6.0              -> v4.6.0
 * [new tag]               v4.6.1              -> v4.6.1
 * [new tag]               v4.6.10-test        -> v4.6.10-test
 * [new tag]               v4.6.2              -> v4.6.2
 * [new tag]               v4.6.3              -> v4.6.3
 * [new tag]               v4.6.4              -> v4.6.4
 * [new tag]               v4.6.5              -> v4.6.5
 * [new tag]               v4.6.6              -> v4.6.6
 * [new tag]               v4.6.7              -> v4.6.7
 * [new tag]               v4.6.8              -> v4.6.8
 * [new tag]               v4.6.9-test         -> v4.6.9-test
Note: checking out 'v4.6.9'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

  git checkout -b <new-branch-name>

HEAD is now at c3314b1c56 Merge pull request #143 from pcengines/rel_v4.6.9
Submodule path '3rdparty/arm-trusted-firmware': checked out 'bfd925139fdbc2e87979849907b34843aa326994'
Submodule path '3rdparty/blobs': checked out '8ad2d6385652e14b6f0d35ab9b474c31ddeb1773'
Submodule path '3rdparty/chromeec': checked out 'ea1a8699e96425806abdd532d04da254ae093f6e'
Submodule path '3rdparty/libgfxinit': checked out '83693c8d7d87f5cebe120abdf25951c9e212b319'
Submodule path '3rdparty/libhwbase': checked out '5e9b1b50e7ac90f68ca2ea798ef656ac863c2851'
Submodule path '3rdparty/vboot': checked out 'ea72ee454aea5e0f378275fe7114cf683b7db938'
Release apu2 build coreboot mainline
Unable to find image 'pcengines/pce-fw-builder:latest' locally
latest: Pulling from pcengines/pce-fw-builder
3a8649ffa174: Pull complete 
7fc1ef040198: Pull complete 
6e5a5d8c482f: Pull complete 
1a6d7a044cdb: Pull complete 
ffb2ffc0b3b6: Pull complete 
30adbdb57e64: Pull complete 
Digest: sha256:06c5e363186fb40da065329b6e7a8c440bbc9a77f4118aee66692ca49e9a5eaf
Status: Downloaded newer image for pcengines/pce-fw-builder:latest
Build coreboot for apu2
/home/coreboot/scripts/pce-fw-builder.sh: line 11: [: missing `]'
cp: cannot stat 'configs/config.pcengines_apu2': No such file or directory
Error: Expected config file (/home/coreboot/coreboot/.config) not present.
Please specify a config file or run 'make menuconfig' to
generate a new config file.
Makefile:128: recipe for target 'real-all' failed
make: *** [real-all] Error 1
cp: cannot stat 'coreboot/build/coreboot.rom': No such file or directory
md5sum: apu2_v4.6.9.rom: No such file or directory
tar: apu2_v4.6.9.rom: Cannot stat: No such file or directory
tar: Exiting with failure status due to previous errors

As a workaround, in scripts/pce-fw-builder.sh, I hard-coded cp configs/pcengines_$1.config .config and removed the check for $legacy (which also causes a syntax error due to missing whitespace).

BIOS write protect option can't be enabled

On apu2d, the Enable BIOS write protect option can't be enabled. It is always "Currently Disabled" after selecting the option. This occurs regardless of whether the WP pins are shorted or not.

Tested on mainline 4.8.0.5 and legacy 4.0.20.

Mainline with pfSense

Now that pfSense has gone through major updates and is running FreeBSD 11.1 are there any known issues with using the Mainline branch of coreboot? I don't have a way to recover, so I'm not brave enough to test moving up from the 4.0.x / Legacy branch.

Reboot/Post hang

apu2c4 with BIOS 4.6.1, 4.6.5, 4.6.6 hangs occasionally during soft reboot/post.

Hard reset clears fault.

4.0.x and 4.5.5 do not show this behaviour.

Reproduce with simple shellscript in tinycore:
date >>reboot.log;sleep 60;reboot

Update: still present in 4.6.8

Serial output is corrupted on boot

It looks like serial console tries to clear the screen during boot, but only manages to rewind it. Makes the welcome prompt corrupted.

E.g.

PC Engines apu2                                                                                                                        
coreboot build 20171130                                                                                                                
BIOS vF10 key now for boot menu                                                                                                        
4080 MB ECC DRAM                                                                                                                       
Select boot device:                                                                                                                    
SeaBIOS (version rel-1.11.0.1-0-g90da88d)                                                                                              
1. ata0-0: SATA SSD ATA-10 Hard-Disk (15272 MiBytes)                                                                                   
2. Payload [memtest]                                                                                                                   
3. Payload [setup]

Booting FILO payload fails

I ran ./apu2/apu2-documentation/scripts/apu2_fw_rel.sh build-ml menuconfig and switched the payload from SeaBIOS to FILO, as I’d like to directly boot a vmlinuz image from a FAT partition.

Unfortunately, the build fails when building for pcengines/apu2 (but e.g. pcengines/apu1 succeeds):

build-ml
    GEN        generated/bootblock.ld
    CP         bootblock/arch/x86/bootblock.ld
    LINK       cbfs/fallback/bootblock.debug
    OBJCOPY    cbfs/fallback/bootblock.elf
    OBJCOPY    bootblock.raw.bin
    CREATE     build/mainboard/pcengines/apu2/cbfs-file.5CJdXr.out (from /release/apu2/coreboot/.config)
    GIT        FILO STABLE
Switched to branch 'master'
Your branch is up-to-date with 'origin/master'.
Fetching origin
Switched to branch 'STABLE'
*** Default configuration is based on 'configs/defconfig'
#
# configuration written to .config
#
#
# configuration written to .config
#
    INSTALL    ../external/FILO/filo/build/libpayload/lib
    INSTALL    ../external/FILO/filo/build/libpayload/include
    INSTALL    ../external/FILO/filo/build/libpayload/bin
    CONFIG     FILO STABLE
Using binary libpayload, nothing to configure
*** Default configuration is based on 'configs/defconfig'
*
* FILO Configuration
*
Build for architecture
> 1. x86 (TARGET_I386)
  2. ARM (TARGET_ARM) (NEW)
choice[1-2]: 1
Include a MultiBoot header (MULTIBOOT_IMAGE) [Y/n/?] (NEW) y
*
* Interface Options
*
Use GRUB like interface (USE_GRUB) [Y/n/?] y
non-interactive interface (NON_INTERACTIVE) [N/y/?] (NEW) n
Command line prompt (PROMPT) [filo] filo
GRUB menu.lst filename (MENULST_FILE) [hda3:/boot/filo/menu.lst] hda3:/boot/filo/menu.lst
Timeout for loading menu.lst (MENULST_TIMEOUT) [0] 0
Use MD5 passwords in menu.lst? (USE_MD5_PASSWORDS) [Y/n/?] y
Support for parsing isolinux.cfg config files (ISOLINUX_PARSER) [Y/n/?] y
*
* Drivers
*
IDE DISK support (IDE_DISK) [N/y/?] n
  New IDE driver (IDE_NEW_DISK) [Y/n/?] y
Use libpayload's storage drivers (LIBPAYLOAD_STORAGE) [N/y/?] (NEW) n
USB Stack (USB_DISK) [Y/n/?] y
NAND Flash support (FLASH_DISK) [N/y/?] n
PCI support (SUPPORT_PCI) [Y/n] y
  Scan all PCI busses (PCI_BRUTE_SCAN) [N/y/?] n
  Sound Support (SUPPORT_SOUND) [N/y] n
Flash memory lockdown (FLASHROM_LOCKDOWN) [N/y/?] (NEW) n
Provide flashupdate command (FLASHUPDATE) [N/y/?] (NEW) n
*
* Filesystems
*
EXT2 filesystem (FSYS_EXT2FS) [Y/n] y
FAT (MSDOS) filesystem (FSYS_FAT) [Y/n] y
JFS (FSYS_JFS) [N/y] n
Minix filesystem (FSYS_MINIX) [N/y] n
ReiserFS (FSYS_REISERFS) [Y/n] y
XFS (FSYS_XFS) [N/y] n
ISO9660 filesystem (FSYS_ISO9660) [Y/n] y
  El Torito bootable CDROMs (ELTORITO) [Y/n/?] y
Compressed RAM filesystem (CRAMFS) (FSYS_CRAMFS) [N/y] n
Squash filesystem (FSYS_SQUASHFS) [N/y] n
CBFS ROM Image filesystem (FSYS_CBFS) [Y/n] y
*
* Loaders
*
Standard Linux Loader (LINUX_LOADER) [Y/n/?] y
Windows CE Loader (WINCE_LOADER) [N/y/?] n
Artec Loader (ARTEC_BOOT) [N/y/?] n
*
* Debugging & Experimental
*
Enable experimental features (EXPERIMENTAL) [Y/n/?] y
DEBUG_ALL (DEBUG_ALL) [N/y] n
DEBUG_ELFBOOT (DEBUG_ELFBOOT) [N/y] n
DEBUG_SEGMENT (DEBUG_SEGMENT) [N/y] n
DEBUG_SYS_INFO (DEBUG_SYS_INFO) [N/y] n
DEBUG_BLOCKDEV (DEBUG_BLOCKDEV) [N/y] n
DEBUG_VFS (DEBUG_VFS) [N/y] n
DEBUG_FSYS_EXT2FS (DEBUG_FSYS_EXT2FS) [N/y] n
DEBUG_PCI (DEBUG_PCI) [N/y] n
DEBUG_LINUXLOAD (DEBUG_LINUXLOAD) [N/y] n
DEBUG_IDE (DEBUG_IDE) [N/y] n
DEBUG_USB (DEBUG_USB) [N/y] n
DEBUG_ELTORITO (DEBUG_ELTORITO) [N/y] n
Developer Tools (DEVELOPER_TOOLS) [Y/n/?] y
#
# configuration written to .config
#
Using binary libpayload, nothing to configure
*
* FILO Configuration
*
Build for architecture
> 1. x86 (TARGET_I386)
  2. ARM (TARGET_ARM)
choice[1-2]: 1
Include a MultiBoot header (MULTIBOOT_IMAGE) [Y/n/?] y
*
* Interface Options
*
Use GRUB like interface (USE_GRUB) [Y/n/?] y
non-interactive interface (NON_INTERACTIVE) [N/y/?] n
Command line prompt (PROMPT) [filo] filo
GRUB menu.lst filename (MENULST_FILE) [hda3:/boot/filo/menu.lst] hda3:/boot/filo/menu.lst
Timeout for loading menu.lst (MENULST_TIMEOUT) [0] 0
Use MD5 passwords in menu.lst? (USE_MD5_PASSWORDS) [Y/n/?] y
Support for parsing isolinux.cfg config files (ISOLINUX_PARSER) [Y/n/?] y
*
* Drivers
*
IDE DISK support (IDE_DISK) [N/y/?] n
  New IDE driver (IDE_NEW_DISK) [Y/n/?] y
Use libpayload's storage drivers (LIBPAYLOAD_STORAGE) [N/y/?] n
USB Stack (USB_DISK) [Y/n/?] y
NAND Flash support (FLASH_DISK) [N/y/?] n
PCI support (SUPPORT_PCI) [Y/n] y
  Scan all PCI busses (PCI_BRUTE_SCAN) [N/y/?] n
  Sound Support (SUPPORT_SOUND) [N/y] n
Flash memory lockdown (FLASHROM_LOCKDOWN) [N/y/?] n
Provide flashupdate command (FLASHUPDATE) [N/y/?] n
*
* Filesystems
*
EXT2 filesystem (FSYS_EXT2FS) [Y/n] y
FAT (MSDOS) filesystem (FSYS_FAT) [Y/n] y
JFS (FSYS_JFS) [N/y] n
Minix filesystem (FSYS_MINIX) [N/y] n
ReiserFS (FSYS_REISERFS) [Y/n] y
XFS (FSYS_XFS) [N/y] n
ISO9660 filesystem (FSYS_ISO9660) [Y/n] y
  El Torito bootable CDROMs (ELTORITO) [Y/n/?] y
Compressed RAM filesystem (CRAMFS) (FSYS_CRAMFS) [N/y] n
Squash filesystem (FSYS_SQUASHFS) [N/y] n
CBFS ROM Image filesystem (FSYS_CBFS) [Y/n] y
*
* Loaders
*
Standard Linux Loader (LINUX_LOADER) [Y/n/?] y
Windows CE Loader (WINCE_LOADER) [N/y/?] n
Artec Loader (ARTEC_BOOT) [N/y/?] n
*
* Debugging & Experimental
*
Enable experimental features (EXPERIMENTAL) [Y/n/?] y
DEBUG_ALL (DEBUG_ALL) [N/y] n
DEBUG_ELFBOOT (DEBUG_ELFBOOT) [N/y] n
DEBUG_SEGMENT (DEBUG_SEGMENT) [N/y] n
DEBUG_SYS_INFO (DEBUG_SYS_INFO) [N/y] n
DEBUG_BLOCKDEV (DEBUG_BLOCKDEV) [N/y] n
DEBUG_VFS (DEBUG_VFS) [N/y] n
DEBUG_FSYS_EXT2FS (DEBUG_FSYS_EXT2FS) [N/y] n
DEBUG_PCI (DEBUG_PCI) [N/y] n
DEBUG_LINUXLOAD (DEBUG_LINUXLOAD) [N/y] n
DEBUG_IDE (DEBUG_IDE) [N/y] n
DEBUG_USB (DEBUG_USB) [N/y] n
DEBUG_ELTORITO (DEBUG_ELTORITO) [N/y] n
Developer Tools (DEVELOPER_TOOLS) [Y/n/?] y
#
# configuration written to .config
#
    MAKE       FILO STABLE
Found libpayload as /release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a
  CC      build/main/grub/grub.o
/bin/sh: 1: -Ibuild: not found
make[2]: *** [/release/apu2/coreboot/payloads/external/FILO/filo/build/main/grub/grub.o] Error 127
make[1]: *** [filo] Error 2
make: *** [filo] Error 2

I tried making the following change in the filo repository:

diff --git i/Makefile w/Makefile
index 68338ba..d5ee468 100644
--- i/Makefile
+++ w/Makefile
@@ -151,7 +151,7 @@ endif
 
 $(obj)/filo: $(OBJS) $(LIBPAYLOAD)
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	CC=$(CC) $(LPGCC) $(OBJS) $(LIBS) -o $@
+	CC="$(CC)" $(LPGCC) $(OBJS) $(LIBS) -o $@
 
 $(obj)/filo.bzImage: $(TARGET) $(obj)/x86/linux_head.o
 	$(OBJCOPY) -O binary $(obj)/x86/linux_head.o [email protected]
@@ -171,11 +171,11 @@ $(KCONFIG_AUTOHEADER): $(src)/.config
 $(OBJS): $(KCONFIG_AUTOHEADER) $(obj)/version.h | libpayload
 $(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
-	CC=$(CC) $(LPGCC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
+	CC="$(CC)" $(LPGCC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
 
 $(obj)/%.S.o: $(src)/%.S
 	printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
-	AS=$(AS) $(LPAS) $(ASFLAGS) -o $@ $<
+	AS="$(AS)" $(LPAS) $(ASFLAGS) -o $@ $<
 
 $(obj)/%.map: $(obj)/%
 	printf "  SYMS    $(subst $(shell pwd)/,,$(@))\n"

While this fixes the immediate issue, I’m now getting errors when linking:

/release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a(pdcdisp.libcurses.o):(.data.serial_acs_map+0x0): multiple definition of `serial_acs_map'
/release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a(tinycurses.libcurses.o):(.data.serial_acs_map+0x0): first defined here
/release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a(pdcdisp.libcurses.o): In function `PDC_gotoyx':
/release/apu2/coreboot/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c:137: multiple definition of `fallback_acs_map'
/release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a(tinycurses.libcurses.o):/release/apu2/coreboot/payloads/libpayload/curses/tinycurses.c:721: first defined here
/release/apu2/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a(pdcdisp.libcurses.o): In function `PDC_gotoyx':
/release/apu2/coreboot/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c:137: multiple definition of `console_acs_map'
[…]

So I’m thinking I might not be on the correct path here.

Do you have any ideas as to why the FILO payload doesn’t build for the apu2?

Thanks,

Switching branches may lead to build failure when dev-build used

Your branch is up to date with 'origin/master'.
fatal: 'rel-1.11.0.5' is not a commit and a branch 'coreboot' cannot be created from it
Makefile:36: recipe for target 'checkout' failed
make[1]: *** [checkout] Error 128
payloads/external/Makefile.inc:85: recipe for target 'payloads/external/SeaBIOS/seabios/out/bios.bin.elf' failed                                                                             
make: *** [payloads/external/SeaBIOS/seabios/out/bios.bin.elf] Error 2

Error when compiling with coreboot 4.6

My environment:

Using built-in specs.                                                                                                                                                                                                                                                         
COLLECT_GCC=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc/bin/i386-elf-gcc                                                                                                                                                                                            
COLLECT_LTO_WRAPPER=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/6.3.0/lto-wrapper                                                                                                                                                                  
Target: i386-elf                                                                                                                                                                                                                                                              
Configured with: ../gcc-6.3.0/configure --prefix=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc --libexecdir=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc/lib --target=i386-elf --disable-werror --disable-shared --enable-lto --enable-plugins --enable-gold --enable-ld=default --disable-libssp --disable-bootstrap --disable-nls --disable-libquadmath --without-headers --disable-threads --enable-interwork --enable-multilib --enable-targets=all --disable-libatomic --disable-libcc1 --disable-decimal-float --enable-languages=c --with-system-zlib --with-gmp=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc --with-mpfr=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc --with-mpc=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc --with-libelf=/home/pkubaj/apu_coreboot/coreboot/util/crossgcc/xgcc --with-pkgversion='coreboot toolchain v1.44 March 3rd, 2017'                                                                                                                                                                                                         
Thread model: single                                                                                                                                                                                                                                                          
gcc version 6.3.0 (coreboot toolchain v1.44 March 3rd, 2017)             

The error I get is:

In file included from spi.h:28:0,                                  
                 from spi_flash.h:26,                              
                 from winbond.c:13:                                
/home/pkubaj/apu_coreboot/coreboot/payloads/external/sortbootorder/sortbootorder/build/libpayload/bin/../include/libpayload.h:332:19: error: conflicting types for built-in function 'log2' [-Werror]                                                                          
 static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; }                                                                  
                   ^~~~
cc1: all warnings being treated as errors                          

APU2 - No EEPROM/flash device found

I'm trying to update from 4.6.1 to 4.6.7, but I keep getting the error below. Any way round this?

[2.4.3-RELEASE][admin@pfsense]/root: flashrom -w /tmp/apu2_v4.6.7.rom -p internal
flashrom v1.0 on FreeBSD 11.1-RELEASE-p7 (amd64)
flashrom is free software, get the source code at https://flashrom.org

Using clock_gettime for delay loops (clk_id: 4, resolution: 2ns).
coreboot table found at 0xcffd6000.
Found chipset "AMD FCH".
Enabling flash write... OK.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.

AMD CCP and TPM as enropy sources

We should provide some documentation and tests to show how entropy sources can be used. We should take a look at entropy sources in light of firewall OSes, which may require entropy to provide various services.

This issue was motivated by discussion from IPFire forum

boot menu key and message dependency

Both boot-menu-message and boot-menu-key is hardcoded and added as a file to CBFS.

Current implementation lets user to add different boot menu message and key, which will lead to displaying false in formation about entering boot menu. The boot menu string should be printed depending on the boot-menu-key too.

APU4 USB port issue

On apu4 boards one may encounter issues with one of two USB 3.0 ports. USB 3.0 stick connected to such malfunctioning port is not detected. Problem is under continuous investigation.

For more information see USB detection tests on regression tests results available at https://pcengines.github.io/ site.

APU2 Serial number is all garbled on 4.6.8

I've finally managed to get onto 4.6.8 with pfSense 2.4.3-RELEASE-p1 on my APU2.

So far I have no problems, LED's are also working again.

Only in the pfSense interface, the serial number is all garbled...
image

Also from the command line:

/bin/kenv -q smbios.system.serial : ▒▒▒▒▒▒▒▒▒▒

I understand that this may be fixed in 4.6.9.

So I'll test that one once it's officially released and confirm.

Give ability to build without distclean

distclean cause removal of SeaBIOS, iPXE and other repos. This can save significant amount of time if repos are already on host. I mainly think about option for dev-build. release requires completely clean .

Forum maintenance long overdue

For lack of a better way, filing this as an issue here. Guys, I know this is apparently not your priority, your hardware is great, but the forum is unusable. Either clean it up and archive it, or replace the zombie software with something that's not spammers' paradise.

E.g., 15/20 threads on the APU forum is spam. Not a productive communication platform for anyone. 👎

pcengines_forum_spam

cannot build 4.6.1

As 4.6.1 is the latest version with working PXE boot on the apu2c4 (I mailed [email protected] about it yesterday), I wanted to customize that image.

Unfortunately, building 4.6.1 fails:

% ./build.sh release v4.6.1 apu2             
Cloning into 'release/coreboot'...           
remote: Counting objects: 15882, done
remote: Finding sources: 100% (196/196)
remote: Total 386032 (delta 49), reused 385941 (delta 49)
Receiving objects: 100% (386032/386032), 84.07 MiB | 10.89 MiB/s, done.
Resolving deltas: 100% (306301/306301), done.
Submodule 'arm-trusted-firmware' (https://review.coreboot.org/arm-trusted-firmware.git) registered for path '3rdparty/arm-trusted-firmware'
Submodule '3rdparty/blobs' (https://review.coreboot.org/blobs.git) registered for path '3rdparty/blobs'
Submodule '3rdparty/chromeec' (https://review.coreboot.org/chrome-ec.git) registered for path '3rdparty/chromeec'
Submodule 'libgfxinit' (https://review.coreboot.org/libgfxinit.git) registered for path '3rdparty/libgfxinit'
Submodule 'libhwbase' (https://review.coreboot.org/libhwbase.git) registered for path '3rdparty/libhwbase'
Submodule 'vboot' (https://review.coreboot.org/vboot.git) registered for path '3rdparty/vboot'
Submodule 'util/nvidia-cbootimage' (https://review.coreboot.org/nvidia-cbootimage.git) registered for path 'util/nvidia/cbootimage'
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/arm-trusted-firmware'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/blobs'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/chromeec'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/libgfxinit'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/libhwbase'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/3rdparty/vboot'...
Cloning into '/home/michael/apu2/pce-fw-builder/release/coreboot/util/nvidia/cbootimage'...
Submodule path '3rdparty/arm-trusted-firmware': checked out '693e278e308441d716f7f5116c43aa150955da31'
Submodule path '3rdparty/blobs': checked out '78a02a7f9d979fcc864638cc40084e662476095f'
Submodule path '3rdparty/chromeec': checked out '11bd4c0f4d11357ab830982d7dec164813c886dd'
Submodule path '3rdparty/libgfxinit': checked out '98a673dc57d90cc79e64c53bd02cfcc1c48ea1aa'
Submodule path '3rdparty/libhwbase': checked out '637f2a4f21ead8ccc45d5256834eb27ce72088db'
Submodule path '3rdparty/vboot': checked out '392211f0358919d510179ad399d8f056180e652e'
Submodule path 'util/nvidia/cbootimage': checked out '64045f993c2cd8989838aeaad3d22107d96d5596'
remote: Counting objects: 5266, done.
remote: Compressing objects: 100% (20/20), done.
remote: Total 5266 (delta 1582), reused 1577 (delta 1574), pack-reused 3672
Receiving objects: 100% (5266/5266), 2.42 MiB | 4.56 MiB/s, done.
Resolving deltas: 100% (3562/3562), completed with 308 local objects.
From https://github.com/pcengines/coreboot
 * [new branch]            alix_early_cbmem    -> pcengines/alix_early_cbmem
 * [new branch]            apu2-uefi-new       -> pcengines/apu2-uefi-new
 * [new branch]            apu5_s1button_ml    -> pcengines/apu5_s1button_ml
 * [new branch]            coreboot-4.0.x      -> pcengines/coreboot-4.0.x
 * [new branch]            coreboot-4.5.x      -> pcengines/coreboot-4.5.x
 * [new branch]            coreboot-4.6.x      -> pcengines/coreboot-4.6.x
 * [new branch]            coreboot-4.6.x-uefi -> pcengines/coreboot-4.6.x-uefi
 * [new branch]            coreboot-4.7.x      -> pcengines/coreboot-4.7.x
 * [new branch]            coreboot-4.7.x-uefi -> pcengines/coreboot-4.7.x-uefi
 * [new branch]            coreboot-4.7.x-wip  -> pcengines/coreboot-4.7.x-wip
 * [new branch]            develop             -> pcengines/develop
 * [new branch]            disable_lpcclk0     -> pcengines/disable_lpcclk0
 * [new branch]            iommu_support       -> pcengines/iommu_support
 * [new branch]            kmalkki-xen-fixes   -> pcengines/kmalkki-xen-fixes
 * [new branch]            master              -> pcengines/master
 * [new branch]            rel_4.8.0.1         -> pcengines/rel_4.8.0.1
 * [new branch]            rel_v4.0.18         -> pcengines/rel_v4.0.18
 * [new branch]            rel_v4.6.10         -> pcengines/rel_v4.6.10
 * [new branch]            rel_v4.6.9          -> pcengines/rel_v4.6.9
 * [new branch]            release             -> pcengines/release
 * [new branch]            rtconf              -> pcengines/rtconf
 * [new branch]            runtime_config      -> pcengines/runtime_config
 * [new branch]            v0.4.1.1-sd-debug   -> pcengines/v0.4.1.1-sd-debug
 * [new branch]            v0.4.1.1-usb-debug  -> pcengines/v0.4.1.1-usb-debug
 * [new tag]               coreboot-4.7.x      -> coreboot-4.7.x
 * [new tag]               v4.0.17             -> v4.0.17
 * [new tag]               v4.5.8              -> v4.5.8
 * [new tag]               v4.6.9              -> v4.6.9
 * [new tag]               v4.7.0              -> v4.7.0
 * [new tag]               apu2b-20160304      -> apu2b-20160304
 * [new tag]               v4.0.1              -> v4.0.1
 * [new tag]               v4.0.1.1            -> v4.0.1.1
 * [new tag]               v4.0.10             -> v4.0.10
 * [new tag]               v4.0.11             -> v4.0.11
 * [new tag]               v4.0.12             -> v4.0.12
 * [new tag]               v4.0.13             -> v4.0.13
 * [new tag]               v4.0.14             -> v4.0.14
 * [new tag]               v4.0.15             -> v4.0.15
 * [new tag]               v4.0.16             -> v4.0.16
 * [new tag]               v4.0.18-test        -> v4.0.18-test
 * [new tag]               v4.0.2              -> v4.0.2
 * [new tag]               v4.0.3              -> v4.0.3
 * [new tag]               v4.0.4              -> v4.0.4
 * [new tag]               v4.0.5              -> v4.0.5
 * [new tag]               v4.0.6              -> v4.0.6
 * [new tag]               v4.0.7              -> v4.0.7
 * [new tag]               v4.0.7.1            -> v4.0.7.1
 * [new tag]               v4.0.7.2            -> v4.0.7.2
 * [new tag]               v4.0.8              -> v4.0.8
 * [new tag]               v4.0.9              -> v4.0.9
 * [new tag]               v4.5.2              -> v4.5.2
 * [new tag]               v4.5.3              -> v4.5.3
 * [new tag]               v4.5.3.1            -> v4.5.3.1
 * [new tag]               v4.5.4              -> v4.5.4
 * [new tag]               v4.5.5              -> v4.5.5
 * [new tag]               v4.5.5.1            -> v4.5.5.1
 * [new tag]               v4.5.5.2            -> v4.5.5.2
 * [new tag]               v4.5.6              -> v4.5.6
 * [new tag]               v4.5.7              -> v4.5.7
 * [new tag]               v4.6.0              -> v4.6.0
 * [new tag]               v4.6.1              -> v4.6.1
 * [new tag]               v4.6.10-test        -> v4.6.10-test
 * [new tag]               v4.6.2              -> v4.6.2
 * [new tag]               v4.6.3              -> v4.6.3
 * [new tag]               v4.6.4              -> v4.6.4
 * [new tag]               v4.6.5              -> v4.6.5
 * [new tag]               v4.6.6              -> v4.6.6
 * [new tag]               v4.6.7              -> v4.6.7
 * [new tag]               v4.6.8              -> v4.6.8
 * [new tag]               v4.6.9-test         -> v4.6.9-test
Note: checking out 'v4.6.1'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

  git checkout -b <new-branch-name>

HEAD is now at 512105cdb1 Merge pull request pcengines/pce-fw-builder#50 from pcengines/rel_v4.6.1
Submodule path '3rdparty/arm-trusted-firmware': checked out 'bfd925139fdbc2e87979849907b34843aa326994'
Submodule path '3rdparty/blobs': checked out '8ad2d6385652e14b6f0d35ab9b474c31ddeb1773'
Submodule path '3rdparty/chromeec': checked out 'ea1a8699e96425806abdd532d04da254ae093f6e'
Submodule path '3rdparty/libgfxinit': checked out '83693c8d7d87f5cebe120abdf25951c9e212b319'
Submodule path '3rdparty/libhwbase': checked out '5e9b1b50e7ac90f68ca2ea798ef656ac863c2851'
Submodule path '3rdparty/vboot': checked out 'ea72ee454aea5e0f378275fe7114cf683b7db938'
Release apu2 build coreboot mainline
Build coreboot for apu2
cp: cannot stat 'configs/config.pcengines_apu2': No such file or directory
Error: Expected config file (/home/coreboot/coreboot/.config) not present.
Please specify a config file or run 'make menuconfig' to
generate a new config file.
Makefile:128: recipe for target 'real-all' failed
make: *** [real-all] Error 1
cp: cannot stat 'coreboot/build/coreboot.rom': No such file or directory
md5sum: apu2_v4.6.1.rom: No such file or directory
tar: apu2_v4.6.1.rom: Cannot stat: No such file or directory
tar: Exiting with failure status due to previous errors

There should be way to force flashing remotely

Right now when we have incompatible firmware booted SMBIOS tables may have different board name then coreboot was built for. This cause flashrom complains. We should be able to force flashing.

APU1 goes straight to OS output in serial console [4.8.0.4]

When flashing an APU1 with 4.8.0.4, no F12 menu is displayed, and there is no apparent way to go into BIOS configuration.

The CMOS pin was shorted to clear any problematic settings, and I also pushed S1 during boot. Flashing with an older BIOS verison (one that I backed up) restored configuration functionality.

apu5 doesn't detect iPXE on mainline

Please add that bug to release notes.

SeaBIOS (version rel-1.11.2-0-gf9626ccXHCI init on dev 00:10.0: regs @ 0xf7f22000, 4 ports, 32 slots, 32 byte contexts
XHCI    extcap 0x1 @ 0xf7f22500
XHCI    protocol USB  3.00, 2 ports (offset 1), def 0
XHCI    protocol USB  2.00, 2 ports (offset 3), def 10
XHCI    extcap 0xa @ 0xf7f22540
EHCI init on dev 00:12.0 (regs=0xf7f26020)
EHCI init on dev 00:13.0 (regs=0xf7f27020)
WARNING - Timeout at i8042_flush:71!
ATA controller 1 at 3010/3020/0 (irq 0 dev 88)
ATA controller 2 at 3018/3024/0 (irq 0 dev 88)
Found 1 lpt ports
Found 4 serial ports
Searching bootorder for: /rom@img/memtest
)
XHCI port pcengines/coreboot#3: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
Searching bootorder for: /pci@i0cf8/usb@12/hub@1/storage@1/*@0/*@0,0
Searching bootorder for: /pci@i0cf8/usb@12/hub@1/usb-*@1
USB MSC vendor='Multiple' product='Card  Reader' rev='1.00' type=0 removable=1
XHCI port pcengines/coreboot#4: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
Device reports MEDIUM NOT PRESENT
scsi_is_ready returned -1
Unable to configure USB MSC drive.
Unable to configure USB MSC device.
xhci_cmd_submit port pcengines/coreboot#4: 0x000002a0, powered, pls 5, speed 0 [ - ]
xhci_alloc_pipe: address device: failed (cc -1)
XHCI port pcengines/coreboot#1: 0x00001203, powered, enabled, pls 0, speed 4 [Super]
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
Searching bootorder for: /pci@i0cf8/usb@10/storage@1/*@0/*@0,0
Searching bootorder for: /pci@i0cf8/usb@10/usb-*@1
USB MSC vendor='Corsair' product='Voyager VEGA' rev='000A' type=0 removable=1
USB MSC blksize=512 sectors=30302208
WARNING - Timeout at xhci_event_wait:740!
xhci_send_pipe: xfer failed (cc -1)
All threads complete.
Scan for option roms

Press ESC for boot menu.

Select boot device:

1. USB MSC Drive Corsair Voyager VEGA 000A
2. Payload [memtest]

Update APU2C BIOS

Hello,

I'm still seeing duplicate printouts over the RS232 connection and it's rather painful to do anything with ncurses... Any tips as to when we can see a sync for the mainline bios shipped by PCEngines? This bug was fixed quite some time ago as per the git tree.

IOMMU group 1 contains all i210s and miniPCIe slots

I've tried to use the new IOMMU support with v4.8.0.3 and v4.8.0.4. The software is use is a Debian Stable with libvirt and qemu-kvm.

When starting a VM where I've assigned a miniPCIe WiFi card, I get:
qemu-system-x86_64: -device vfio-pci,host=04:00.0,id=hostdev0,bus=pci.0,addr=0x8,rombar=1: vfio error: 0000:04:00.0: group 1 is not viable

The cause of this error is that all the i210s and the miniPCIe slots are assigned to the same IOMMU group (1):

root@apu:~# dmesg | grep -i iommu
[    2.187590] AMD-Vi: IOMMU performance counters supported
[    2.188848] iommu: Adding device 0000:00:00.0 to group 0
[    2.189232] iommu: Adding device 0000:00:02.0 to group 1
[    2.189323] iommu: Adding device 0000:00:02.2 to group 1
[    2.189380] iommu: Adding device 0000:00:02.3 to group 1
[    2.189423] iommu: Adding device 0000:00:02.4 to group 1
[    2.189466] iommu: Adding device 0000:00:02.5 to group 1
[    2.189705] iommu: Adding device 0000:00:08.0 to group 2
[    2.190015] iommu: Adding device 0000:00:10.0 to group 3
[    2.190226] iommu: Adding device 0000:00:11.0 to group 4
[    2.190454] iommu: Adding device 0000:00:13.0 to group 5
[    2.190818] iommu: Adding device 0000:00:14.0 to group 6
[    2.190890] iommu: Adding device 0000:00:14.3 to group 6
[    2.190933] iommu: Adding device 0000:00:14.7 to group 6
[    2.191292] iommu: Adding device 0000:00:18.0 to group 7
[    2.191394] iommu: Adding device 0000:00:18.1 to group 7
[    2.191465] iommu: Adding device 0000:00:18.2 to group 7
[    2.191509] iommu: Adding device 0000:00:18.3 to group 7
[    2.191558] iommu: Adding device 0000:00:18.4 to group 7
[    2.191603] iommu: Adding device 0000:00:18.5 to group 7
[    2.191639] iommu: Adding device 0000:01:00.0 to group 1
[    2.191679] iommu: Adding device 0000:02:00.0 to group 1
[    2.191741] iommu: Adding device 0000:03:00.0 to group 1
[    2.191773] iommu: Adding device 0000:04:00.0 to group 1
[    2.191836] AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40
[    2.201092] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4 counters/bank).
[    4.223108] AMD IOMMUv2 driver by Joerg Roedel <[email protected]>
root@apu:~# lspci 
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1566
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1567
00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 156b
00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:02.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:02.4 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:02.5 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:08.0 Encryption controller: Advanced Micro Devices, Inc. [AMD] Device 1537
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 11)
00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [IDE mode] (rev 39)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 39)
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 42)
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 11)
00:14.7 SD Host controller: Advanced Micro Devices, Inc. [AMD] FCH SD Flash Controller (rev 01)
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1580
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1581
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1582
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1583
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1584
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1585
01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
02:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
03:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
04:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter

I've looked at the coreboot source, but havn't found where this is configured. I've got the flash recovery module, so testing any possible fixes is easy.

bugs in docs/building-firmware.md

There is a wrong path to coreboot root directory in sortbootorder Makefile. The paper should consider checking out to coreboot-4.0.x branch before making sortbootorder.
Flag is missing in the command:
./build/cbfstool ./build/coreboot.rom add-payload -f /memtest86plus/memtest -n img/memtest - payload
./build/cbfstool ./build/coreboot.rom add-payload -f /memtest86plus/memtest -n img/memtest -t payload

Building release removes more files than neccessary

Doing release build removes previous .rom files, as well as removes without warning custom-made changes to everything under release directory, e.g. builds tested with dev-build.

release() {
    if [ -d release ]; then
        sudo rm -rf release
    fi
...

Removing just release/coreboot would be sufficient. It also gives ability to have different versions of coreboot built for later needs in one place, without rebuilding or copying them elsewhere.

apu5

Hi

Were can I buy the corresponding hardware "apu5" which works with the release apu5 v4.8.0.1 from here?

[4.8.0.5] Enabling ECC on PC Engines platforms

I noted in the release notes of 4.8.0.5 the following:

ECC exclusion range, ECC now works properly. For details see also 3mdeb blog post about enabling ECC on PC Engines apu platforms.

However, I've had a look at that blog post, and if I'm not mistaken, it only explains how to test it in MemTest86, not specifically how to enable it.

So I just wanted to check, is there something specific that I need to do to enable ECC as suggested in the release notes? Or should it just work in the latest firmware?

Some PCIe cards may not be detected on certain OSes

mPCIe extension cards often require correct kernel modules/drivers and/or firmware blobs. If the card is not detected, be sure to check whether all needed modules and drivers are present on the system.

Also have a look at the mPCIe capabilities and connection to mPCIe ports on apu boards:
https://github.com/pcengines/apu2-documentation/blob/master/docs/APU_mPCIe_capabilities.md
Certain cards may require USB signals or SIM cards signals connected to the port. Be sure to match the mPCIe card requirements with correct mPCIe port to enable all features of the module.

An error in docs/building_firmware.md

This command doesn't work:

docker run --rm \
   -v ${PWD}:/workdir \
   -t -i pc-engines/apu2 bash

You need to run:

docker run --rm \
   -v ${PWD}:/workdir \
   -t -i pc-engines/apu2b bash

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