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This repository contains simulation files and other relevant files on the On-chip clock multiplier using PLL (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v) IP worked on in the VSD Online Internship.

The target is to design a On-chip clock multiplier using the osu180nm technology node. The specifications are provided from VSD Corporation Pvt. Ltd. The On-chip clock multiplier is present in almost all synchronous processor chips (Integrated circuits).

• 1. Introduction to On-chip clock multiplier
• 2. Theory
• 3. Specification List
• 4. EDA Tools Used
• 5. Pre-layout Simulations
• 6. Post-layout and Simulations
• 7. Future work
• 8. Author
• 9. Contributors
• 10. Acknowledgments
• 11. Contact Information -

The clock generator is one of the most crucial part in synchronous processor & probably most susceptible after power lines which can cause failure of entire circuitry if not designed properly.

The phase locked loop or PLL is a circuit block that is widely used in radio frequency or wireless applications.

In view of its usefulness, the phase locked loop or PLL is found in many wireless, radio, and general electronic items from mobile phones to broadcast radios, televisions to Wi-Fi routers, walkie talkie radios to professional communications systems etc.

the circuit simulated here uses PLL block to get desired frequency at it’s output (which is 8 times to that of input frequency provided). This IP block can be used for clock distribution for processor chip.

The design has been built using open-source EDA tools. The library used is osu180nm.

1. Ngspice
2. Magic

The complete circuit of PLL is built hierarchically using the following subcircuit blocks.

Fig: Block Diagrm of PLL Design.

Fig: Input-Output waveforms from Pre-layout Simulation.

Pre-layout Simulation Results

Fig: Layout of Phase Frequency Detector (PFD) or Phase Detector (PD)

Fig: Input-Output waveforms of Phase Frequency Detector (PFD) or Phase Detector (PD)

Fig: Layout of Voltage Controlled Oscillator (VCO).

Fig: Input-Output waveforms of Voltage Controlled Oscillator (VCO).

Fig: Layout of Frequency Divider by 2.

Fig: Input-Output waveforms of Frequency Divider by 2.

Fig: Layout of Frequency Divider by 8.

Fig: Input-Output waveforms of Frequency Divider by 8.

Note: As there were limitaions for for layout of capacitor in OSU180 tech file, I'm unable to make layout of Low Pass Filter. However, using more mature & advanced nodes & PDK tech file, it can be made on silicon.

1. Porting this IP on lower technology nodes using advance PDK's where capacitor fabrication is realizable
2. Area Efficient Design Improvements.
3. Improvements for Power Reduction.
4. Improvements of accuracy, jitter & dead zone.

• Paras Gidd, M.Tech.( Microelectronics ), Manipal Institute of Technology,(MAHE), [email protected]

• Paras Gidd
• Kunal Ghosh
• Philipp Gühring

• Kunal Ghosh, Co-founder VSD Corp. Pvt. Ltd.

• Philipp Gühring, Software Architect, LibreSilicon Association.

• FOSSEE Team, IIT Bombay

• R. Timothy Edwards, Open Circuit Design

• Gerald Topalli - who helped me with basics of PLL & phase locking.

  I would also like to thank research fellows for extending their help and guidance during the research internship program. They have their own projects & if you are interested in those projects have a look in the links provided below.

• Sheryl Serrao - 10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Reuel Reuben - SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

• Ananya Ghorai - 10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Yash Kumar - SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

• Neethu Johny - 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Ashutosh Sharma - 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

And Last but not least, I would like to thank my Parents & Teachers who directly & indirectly helped me & their contribution is of great value for me.

• Paras Gidd, M.Tech.( Microelectronics ), Manipal Institute of Technology,(MAHE), [email protected]
• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - [email protected]
• Philipp Gühring, Software Architect, LibreSilicon Association - [email protected]