Hi,

I am trying to use the Raptor tool and am interested in turning on the "timing_flow analytic" option. According to the document, it is supposed to do an analytical placement (as an initial placement) followed by a simulated annealing process (as a refinement step).

Whenever I add this option to the .tcl file, raptor errors in the VPR stage, telling me there is no command line option called "enable_cascade_placer". Then, I examined the code in the original PR called "Adding analytical-based initial placer" and saw this option was added to multiple files:

1. include/read_verilog/OpenFPGA/vpr/src/base/SetupVPR.cpp
2. include/read_verilog/OpenFPGA/vpr/src/base/read_options.cpp
3. include/read_verilog/OpenFPGA/vpr/src/base/read_options.h\
4. include/read_verilog/OpenFPGA/vpr/src/base/vpr_types.h

However, none of the above files exist in the master branch, which might be causing the issue.
Can you please help me to figure out how to use this option? I really appreciate your time and response in advance.

Add add_subdirectory(pin_c) to Backend/CMakeLists.txt and resolve all the compilation errors from pin_c.
Submit a working PR.

IPO is disabled in non-production build at Raptor level.

┆Issue is synchronized with this Jira Bug by Unito

OpenFPGA11541 is no longer needed (for over 2 months already)

┆Issue is synchronized with this Jira Bug by Unito

This was a temporary version to confirm bitstream generation, it is not needed anymore, it takes disk space

Describe the bug
A clear and concise description of what the bug is.

• Continous Integration

To Reproduce
Steps to reproduce the behavior:

1. Clone repository and checkout commit id: 94966a5
2. Execute a test case or your own example: https://github.com/RapidSilicon/OpenFPGA_RS2/runs/6750446190?check_suite_focus=true
3. See error

Expected behavior
Should have no such errors.
Recommend to double check the package name for tcllib-dev in Ubuntu-latest in Github Machines (Currently it is taken from the package list for Ubuntu 18.04)

Screenshots

[ 91%] [FLEX][VerilogLex] Building scanner with flex 2.6.4
[ 91%] Building CXX object OpenSTA/CMakeFiles/OpenSTA.dir/app/StaMain.cc.o
/home/runner/work/OpenFPGA_RS2/OpenFPGA_RS2/OpenSTA/app/StaMain.cc:19:10: fatal error: tcl.h: No such file or directory
   19 | #include <tcl.h>
      |          ^~~~~~~
compilation terminated.
make[3]: *** [OpenSTA/CMakeFiles/OpenSTA.dir/build.make:155: OpenSTA/CMakeFiles/OpenSTA.dir/app/StaMain.cc.o] Error 1
make[2]: *** [CMakeFiles/Makefile2:2207: OpenSTA/CMakeFiles/OpenSTA.dir/all] Error 2
make[1]: *** [Makefile:136: all] Error 2
make: *** [Makefile:38: compile] Error 2

Enviornment (please complete the following information):

• OS:

• Tool:

• Version:

Additional context
Add any other context about the problem here.

Is your feature request related to a problem? Please describe.
Currently, the PRs created by dependabot still require code owners's review and approval.
However, this may eat a lot of time from engineers, since this project:

• integrates OpenFPGA and OpenSTA, check the correctness of the integration
• check compilation compatibility for the submodules. Correctness of OpenFPGA and OpenSTA should be already checked in their own regression tests

Describe the solution you'd like

• I have already enable auto-merge and remove any protection on main branch in github repo settings
• See how to enable this feature in the dependabot.yml