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tutorials's Introduction

OpenRISC Tutorials

These are tutorials for the OpenRISC processor. The simulations run on different FPGA boards and simulators. Hence, the different tutorials have different requirements, which you can find in the list below. If you have downloaded the tutorials and are new to OpenRISC, you probably want the real quick start.

Quick Start

This is the real quick start if you have downloaded and extracted the tutorials. The output files are already part of what you have downloaded, but you still need some tools. You can install prebuilt versions of them:

./bootstrap-quick-start.sh

This downloads all free and open tools. Unfortunately, you will still need to install closed (but free) tools from the FPGA vendors:

You can now start with the tutorials.

Set Environment

Once you have installed the dependencies, you can do the following tutorials. For convenience, you can set the environment variables for all tools downloaded and installed automatically:

source environment.sh

Tutorials

There are simulations and FPGA boards supported, and some general tutorials help you working with the OpenRISC ecosystem.

Simulations

FPGA Boards

Debug Environment

The OpenRISC cpu, simulator and toolchain provide a full debugging environment with gdb and OpenOCD. At a low level this is provided with adv_debug_sys which provides jtag interface for OpenOCD to talk to. Much debugging can be done directly in OpenOCD. GDB communicates with OpenOCD to provide a familiar debugging environment for programmers. For more details see:

Tools (partially required)

OpenOCD

The OpenOCD version delivered with the Linux distributions is most probably outdated. Hence, you can quickly install a current version inside the tutorials:

make openocd-download

In case you cannot start openocd, you may rebuilt it also:

make openocd-build

Toolchain

The OpenRISC software tool chain consists of all the tools require to compile and manipulate software for the platform. Specifically, the tool chain which is considered the development version will be used to compile code to run on the "bare metal" system. That is, with no underlying operating system.

You will need the toolchain if you want to compile software. The quick way just to play around with this tutorials is to run from the base path:

make toolchain-baremetal

FuseSoC

FuseSoC is an automated build environment and package manager for OpenRISC. You can install it as described here (recommended) or use the prebuilt binaries:

make fusesoc-download

You can also built it in this tutorial path:

make fusesoc-build

or1ksim

or1ksim is the OpenRISC instruction set simulator. You can download the prebuilt binary:

make or1ksim-download

or build it here:

make or1ksim-build

Linux

There is a prebuilt Linux image you can simply download:

make linux-download

Altera Quartus Prime

This is the software which compiles RTL and ultimately generates an FPGA programming file. Unfortunately this software is closed source, extremely large, and requires registration to download. However, it is required.

For downloading the free version, visit the Altera website and download the latest version of Quartus Prime Lite. It is 4.5GB in size and will obviously take a while to download. Once it is downloaded, extract it and run the setup.sh file in there. Install it to any location (e.g. /opt/altera/lite).

After installation add the following path (corrected for your installation) to the search path:

export PATH=/opt/altera/lite/15.1/quartus/bin/:$PATH

Note: Make sure you select to include the Cyclone IV E device families during installation.

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tutorials's Issues

or1k-sim getting "Killed" halfway of process

Hi,

I am new to OpenRISC.
I am experimenting with the or1ksim instruction set simulator.
Actually I am following this tutorial, in an attempt to just run the "hello.elf":

https://github.com/openrisc/tutorials/tree/master/or1ksim

When I am running the or1k-sim -f or1ksim.cfg hello.elf command, I get the following output and the process is killed:

Seeding random generator with value 0x10358439
Insn MMU 0KB: 1 ways, 64 sets, entry size 1 bytes
Data MMU 0KB: 1 ways, 64 sets, entry size 1 bytes
Ethernet TAP type
Warning: ./or1ksim.cfg: Unrecognized parameter: sockif at line 713; ignored.
Verbose on, simdebug off, interactive prompt off
Machine initialization...
Clock cycle: 10ns
No data cache.
No instruction cache.
BPB simulation off.
BTIC simulation off.
Or1ksim 2012-04-27
Building automata... done, num uncovered: 0/215.
Parsing operands data... done.
Killed

Do you have any ideas on what might be the problem here?

I am running or1ksim on Ubuntu 18.04.4 LTS.
I really need an answer on this. Thank you in advance for your help.

Kind regards,
Nassos

Or1k load vmlinux with error "Kernel panic - not syncing: No working init found."

hi, openrisc experts:
I am new to openrisc.
So first I am start from this tutorials.
After installed all the tooltain and tools, I copy the toolchain from tutorials directory to /opt/toolchain/or1k-elf.
I already success load the vmlinux from this tutorials in or1ksim.

Now I want to build the kernel from scratch.
First I download linux as:
git clone https://github.com/openrisc/linux.git
Then build vmlinux with below command:
cd linux; make defconfig; make
I am using tcsh to build linux, and already setenv for ARCH and PREFIX
setenv PREFIX /opt/toolchain/or1k-elf
setenv ARCH openrisc
setenv CROSS_COMPILE or1k-elf-

But I failed with below error:
This architecture does not have kernel memory protection.
Kernel panic - not syncing: No working init found. Try passing init= option to kernel. See Linux Documentation/admin-guide/init.rst for guidance.

The whole log message is below:
seeding random generator with value 0x60afebfd
Insn MMU 0KB: 1 ways, 64 sets, entry size 1 bytes
Data MMU 0KB: 1 ways, 64 sets, entry size 1 bytes
Ethernet TAP type
Warning: ./or1ksim-linux.cfg: Unrecognized parameter: sockif at line 714; ignored.
Verbose on, simdebug off, interactive prompt off
Machine initialization...
Clock cycle: 10ns
No data cache.
No instruction cache.
BPB simulation off.
BTIC simulation off.
Or1ksim 2012-04-27
Building automata... done, num uncovered: 0/215.
Parsing operands data... done.
Warning: Failed to set TAP device tap0: Operation not permitted
UART at 0x90000000
Resetting Tick Timer.
Resetting Power Management.
Resetting PIC.
Starting at 0x00000000
loadcode: filename vmlinux startaddr=00000000 virtphy_transl=00000000
Not COFF file format
ELF type: 0x0002
ELF machine: 0x005c
ELF version: 0x00000001
ELF sec = 30
Section: .text, vaddr: 0xc0000000, paddr: 0x0 offset: 0x00002000, size: 0x002ffb1c
Section: .rodata, vaddr: 0xc0300000, paddr: 0x300000 offset: 0x00302000, size: 0x000375c0
Section: .eh_frame, vaddr: 0xc03375c0, paddr: 0x3375c0 offset: 0x003395c0, size: 0x000570a4
Section: __ksymtab, vaddr: 0xc038e664, paddr: 0x38e664 offset: 0x00390664, size: 0x00004d78
Section: __ksymtab_gpl, vaddr: 0xc03933dc, paddr: 0x3933dc offset: 0x003953dc, size: 0x000036a0
Section: __ksymtab_strings, vaddr: 0xc0396a7c, paddr: 0x396a7c offset: 0x00398a7c, size: 0x00012bde
Section: __param, vaddr: 0xc03a965c, paddr: 0x3a965c offset: 0x003ab65c, size: 0x0000035c
Section: __modver, vaddr: 0xc03a99b8, paddr: 0x3a99b8 offset: 0x003ab9b8, size: 0x00000648
Section: .data, vaddr: 0xc03aa000, paddr: 0x3aa000 offset: 0x003ac000, size: 0x0001ae40
Section: __ex_table, vaddr: 0xc03c4e40, paddr: 0x3c4e40 offset: 0x003c6e40, size: 0x00000998
Section: .notes, vaddr: 0xc03c57d8, paddr: 0x3c57d8 offset: 0x003c77d8, size: 0x00000024
Section: .head.text, vaddr: 0xc03c6000, paddr: 0x3c6000 offset: 0x003c8000, size: 0x00004000
Section: .init.text, vaddr: 0xc03ca000, paddr: 0x3ca000 offset: 0x003cc000, size: 0x00018cc8
Section: .init.data, vaddr: 0xc03e2ce0, paddr: 0x3e2ce0 offset: 0x003e4ce0, size: 0x00001d9c
Section: .data..percpu, vaddr: 0xc03e6000, paddr: 0x3e4a7c offset: 0x003e6a7c, size: 0x00000000
WARNING: sim_init: Debug module not enabled, cannot start remote service to GDB
****************** counters reset ******************
cycles 121944, insn #97757
****************** counters reset ******************
Compiled-in FDT at (ptrval)
Linux version 4.15.0-rc8-16375-g0fedb76 (jiemin@jiemin-ubuntu) (gcc version 5.2.0 (GCC)) #1 Sun Feb 4 15:53:36 CST 2018
CPU: OpenRISC-12 (revision 1) @20 MHz
-- dcache disabled
-- icache disabled
-- dmmu: 64 entries, 1 way(s)
-- immu: 64 entries, 1 way(s)
-- additional features:
-- power management
-- timer
setup_memory: Memory: 0x0-0x2000000
Setting up paging and PTEs.
map_ram: Memory: 0x0-0x2000000
itlb_miss_handler (ptrval)
dtlb_miss_handler (ptrval)
OpenRISC Linux -- http://openrisc.io
Built 1 zonelists, mobility grouping off. Total pages: 4080
Kernel command line: earlycon
earlycon: ns16550a0 at MMIO 0x90000000 (options '115200')
bootconsole [ns16550a0] enabled
Dentry cache hash table entries: 4096 (order: 1, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 0, 8192 bytes)
Sorting __ex_table...
Memory: 28464K/32768K available (3070K kernel code, 108K rwdata, 680K rodata, 128K init, 94K bss, 4304K reserved, 0K cma-reserved)
mem_init_done ...........................................
NR_IRQS: 32, nr_irqs: 32, preallocated irqs: 0
clocksource: openrisc_timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 95563022313 ns
40.00 BogoMIPS (lpj=200000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 0, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 0, 8192 bytes)
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 256 (order: -2, 3072 bytes)
random: get_random_u32 called from 0xc0183de8 with crng_init=0
NET: Registered protocol family 16
clocksource: Switched to clocksource openrisc_timer
NET: Registered protocol family 2
TCP established hash table entries: 2048 (order: 0, 8192 bytes)
TCP bind hash table entries: 2048 (order: 0, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
UDP hash table entries: 512 (order: 0, 8192 bytes)
UDP-Lite hash table entries: 512 (order: 0, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
workingset: timestamp_bits=30 max_order=12 bucket_order=0
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
console [ttyS0] disabled
90000000.serial: ttyS0 at MMIO 0x90000000 (irq = 2, base_baud = 1250000) is a 16550A
console [ttyS0] enabled
console [ttyS0] enabled
bootconsole [ns16550a0] disabled
bootconsole [ns16550a0] disabled
libphy: Fixed MDIO Bus: probed
NET: Registered protocol family 17
devtmpfs: mounted
Freeing unused kernel memory: 128K
This architecture does not have kernel memory protection.
Kernel panic - not syncing: No working init found. Try passing init= option to kernel. See Linux Documentation/admin-guide/init.rst for guidance.

Can you kindly provide suggestion to help me to go through this error?

Thanks.

Add Atlys Board

Pretty please :-P

It should already be supported by FuseSoC right?

Generate static web content

I think all markdown pages should probably be converted into a static website that can be created after every release. Needs some more thought how to do it properly.

Getting error when opening the OpenOCD

Hello All,

I have installed the OpenOCD from the link given in the Makefile of the tutorials (https://github.com/openrisc/tutorials/releases/download/2016.1/openocd.tgz). I have programmed the De0_ano board with the de0_nano.jic file generated by the FuseSoC using the Altera programmer. Then, I tried to start the OpenOCD using the command given in the tutorials :
openocd -s ${OPENOCD}/share/openocd/scripts/ -f interface/altera-usb-blaster.cfg -f ../or1k-dev.tcl

But, when I run this, I am getting the following errors. Can someone please help me with this ?
$sudo ../../tools/openocd/bin/openocd -s ../../tools/openocd/share/openocd/scripts/ -f interface/altera-usb-blaster.cfg -f ../or1k-dev.tcl
Open On-Chip Debugger 0.10.0-dev-00247-g73b676c (2016-03-20-13:27)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
Info : vjtag tap selected
Info : adv debug unit selected
Info : Option 7 is passed to adv debug unit
Info : set servers polling period to 1ms
Info : No lowlevel driver configured, will try them all
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Error: ftdi_read_data: usb bulk read failed
Info : TAP or1200.cpu does not have IDCODE
Info : TAP auto0.tap does not have IDCODE
Info : TAP auto1.tap does not have IDCODE
Info : TAP auto2.tap does not have IDCODE
Info : TAP auto3.tap does not have IDCODE
Info : TAP auto4.tap does not have IDCODE
Info : TAP auto5.tap does not have IDCODE
Info : TAP auto6.tap does not have IDCODE
Info : TAP auto7.tap does not have IDCODE
Info : TAP auto8.tap does not have IDCODE
Info : TAP auto9.tap does not have IDCODE
Info : TAP auto10.tap does not have IDCODE
Info : TAP auto11.tap does not have IDCODE
Info : TAP auto12.tap does not have IDCODE
Info : TAP auto13.tap does not have IDCODE
Info : TAP auto14.tap does not have IDCODE
Info : TAP auto15.tap does not have IDCODE
Info : TAP auto16.tap does not have IDCODE
Info : TAP auto17.tap does not have IDCODE
Info : TAP auto18.tap does not have IDCODE
Info : TAP auto19.tap does not have IDCODE
Warn : Unexpected idcode after end of chain: 21 0x00000000
Warn : Unexpected idcode after end of chain: 53 0x00000000
Warn : Unexpected idcode after end of chain: 85 0x00000000
Warn : Unexpected idcode after end of chain: 117 0x00000000
Warn : Unexpected idcode after end of chain: 149 0x00000000
Warn : Unexpected idcode after end of chain: 181 0x00000000
Warn : Unexpected idcode after end of chain: 213 0x00000000
Warn : Unexpected idcode after end of chain: 245 0x00000000
Warn : Unexpected idcode after end of chain: 277 0x00000000
Warn : Unexpected idcode after end of chain: 309 0x00000000
Warn : Unexpected idcode after end of chain: 341 0x00000000
Warn : Unexpected idcode after end of chain: 373 0xfffff800
Error: double-check your JTAG setup (interface, speed, ...)
Error: Trying to use configured scan chain anyway...
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x00000000"
Error: auto0.tap: IR capture error; saw 0x0003 not 0x0001
Warn : Bypassing JTAG setup events due to errors
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Error: Couldn't read the CPU state
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 1 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 2 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 3 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 4 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 5 of 5
Error: Could not re-establish communication with target
Error: Error while calling or1k_is_cpu_running
Polling target or1200.cpu failed, trying to reexamine
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Error: Couldn't read the CPU state
Examination failed, GDB will be halted. Polling again in 100ms
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 1 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 2 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 3 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 4 of 5
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : Debug IF CPU control reg read failure.
Warn : Resetting JTAG TAP state and reconnectiong to debug IF.
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Warn : ...attempt 5 of 5
Error: Could not re-establish communication with target
Error: Error while calling or1k_is_cpu_running
Polling target or1200.cpu failed, trying to reexamine
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Error: Couldn't read the CPU state
Examination failed, GDB will be halted. Polling again in 300ms
Halting processor
Warn : Target was in unknown state when halt was requested
Error: No VJTAG TAP instance found !
Error: TAP initialization failed
Error: Impossible to stall the CPU

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