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Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

License: Other

C++ 88.04% Shell 0.16% Verilog 6.27% Python 5.26% Makefile 0.22% Dockerfile 0.05%

verilog iroha fpga programming-language

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hiromi-mi ericyao2013 robtaylor simrit1

karuta's Issues

Path to make actual changes in HLS

IMHO, HLS technology is stuck with C/C++ for decades while software industry adopts per ecosystem new programming languages with new technology and they actually bring us improved development experience.
So, the objective of this project is to explore the potential of HLS without restriction of C/C++ by designing a new language. New language should allow users to describe essentials of circuits easily.
Here are some options we might consider:

Continue on the current efforts to improve the quality and features.
This is current plan anyway for now. However, it will take very long time to achieve production quality. Possibly I can get ask more investment in some future when I will be more confident with the direction and implementation.
Build attractive IPs easily and showcase them.
Attractive applications might be useful to explain the potential. This will also drive quality improvement.
Let someone reuse the idea.
If someone find this concept useful and implement similar language for their ecosystem, it would be nice for us as well.
Let someone fork the code.
As Karuta (and Iroha) is released under an Open Source license, someone with more development resource than us can improve it to production quality
Let someone buy the code.
This is also fine. The buyer can optionally get an engineer :p

switch statement

the docs say wip are they implemented?

#define or similar

for constants

Better testing system

Testbenches for Karuta's RTL generation also needs better abstraction (weak against changes and hard to reuse).
One possible idea is to implement a language and transpiler for this purpose.

How to write an infinite loop ?

I wrote fib.n

object Fib = Kernel.clone();
object Global.Fib = Fib;

int Fib.param  = 0;
int Fib.result = 0;

def Fib.fib(){
  int curr;
  int next;
  int prev;
  int i;
  curr = 0;
  next = 1;
  for (i = 0; i < param; ++i) {
    prev = curr;
    curr = next;
    next = next + prev;
  }
  result = curr;
}

def Fib.main() {
  int *req = 0;
  int *in  = 1;
  int *out = 2;
  while(1) {
    if (*req != 0) {
      param = *in;
      fib();
      *out = result;
    }
  }
}
if (Env.isMain()) {
  Fib.setDump("./tmp/fib");
  Fib.compile();
  Fib.writeHdl("fib.v");
  Fib.writeHdl("fib.cpp");
}

generated fib.v

// 0.1.9

module mod_main(clk, rst, addr_o, write_en_o, data_o, data_i);
  input clk;
  input rst;
  // EXTERNAL_RAM
  output [31:0] addr_o;
  output write_en_o;
  output [31:0] data_o;
  input [31:0] data_i;

  reg [31:0] addr_o;
  reg write_en_o;
  reg [31:0] data_o;

  reg [31:0]  r1_main;
  reg [31:0]  r3_main;
  reg [-1:0]  r7_main;
  reg  r6_main;
  reg [31:0]  r14_main;
  reg [31:0]  reg_t3_v1;
  reg [31:0]  reg_t2_v3;
  reg [31:0]  reg_t4_v4;
  reg [31:0]  reg_t4_v5;
  reg [31:0]  reg_t3_v6;
  reg [31:0]  reg_t2_v9;
  reg  r6_main_v17;
  reg [31:0]  r9_main_v18;
  reg  reg_t9;
  reg  reg_t10;
  wire  wire_t12;
  wire  wire_t13;
  wire [31:0]  wire_t14;
  wire [31:0]  wire_t15;
  wire [31:0]  wire_t16;
  wire  wire_t17;
  wire [31:0]  wire_t18;
  wire [31:0]  wire_t19;

  // declare state begin
 `define S_0 0
 `define S_65 65
 `define S_3 3
 `define S_13 13
 `define S_66 66
 `define S_20 20
 `define S_63 63
 `define S_50 50
 `define S_54 54

  reg [7:0] cur_st;
  // declare state end

  // resources begin
  // branch_1


  // eq_5

  // inv_6

  // gt_8
  wire gt_8_d0;
  wire [31:0] gt_8_s0;
  wire [31:0] gt_8_s1;
  assign gt_8_s0 = (cur_st == `S_50) ? r9_main_v18 : (0);
  assign gt_8_s1 = (cur_st == `S_50) ? wire_t16 : (0);
  assign gt_8_d0 = (gt_8_s0 > gt_8_s1);

  // add_9
  wire [31:0] add_9_d0;
  wire [31:0] add_9_s0;
  wire [31:0] add_9_s1;
  assign add_9_s0 = (cur_st == `S_54) ? reg_t3_v1 : (0);
  assign add_9_s1 = (cur_st == `S_54) ? reg_t2_v3 : (0);
  assign add_9_d0 = (add_9_s0 + add_9_s1);

  // selector_12

  // sram_if_13

  // add_15
  wire [31:0] add_15_d0;
  wire [31:0] add_15_s0;
  wire [31:0] add_15_s1;
  assign add_15_s0 = (cur_st == `S_54) ? r1_main : (0);
  assign add_15_s1 = (cur_st == `S_54) ? 32'd1 : (0);
  assign add_15_d0 = (add_15_s0 + add_15_s1);

  // resources end

  // insn wires begin
  assign o_insn_117_0 = data_i;
  wire [-1:0] o_insn_118_0; // id:118
  assign o_insn_118_0 = data_i;
  wire o_insn_5_0; // id:5
  assign o_insn_5_0 = r7_main==32'd0;
  wire o_insn_6_0; // id:6
  assign o_insn_6_0 = !wire_t12;
  assign o_insn_120_0 = data_i;
  wire [31:0] o_insn_121_0; // id:121
  assign o_insn_121_0 = data_i;
  assign o_insn_123_0 = data_i;
  wire [31:0] o_insn_110_0; // id:110
  assign o_insn_110_0 = reg_t9 ? r14_main : reg_t3_v6;
  wire [31:0] o_insn_113_0; // id:113
  assign o_insn_113_0 = reg_t10 ? reg_t2_v9 : r3_main;
  wire [31:0] o_insn_116_0; // id:116
  assign o_insn_116_0 = r6_main ? reg_t4_v5 : reg_t4_v4;
  wire o_insn_78_0; // id:78
  assign o_insn_78_0 = gt_8_d0;
  wire [31:0] o_insn_85_0; // id:85
  assign o_insn_85_0 = add_9_d0;
  wire [31:0] o_insn_89_0; // id:89
  assign o_insn_89_0 = add_15_d0;
  // insn wires end

  // insn result wires begin
   assign wire_t12 = o_insn_5_0;
   assign wire_t13 = o_insn_6_0;
   assign wire_t14 = o_insn_110_0;
   assign wire_t15 = o_insn_113_0;
   assign wire_t16 = o_insn_116_0;
   assign wire_t17 = o_insn_78_0;
   assign wire_t18 = o_insn_85_0;
   assign wire_t19 = o_insn_89_0;
  // insn result wires end

  // sub state regs begin
  // sub state regs end
  always @(posedge clk) begin
    if (rst) begin
      cur_st <= `S_0;
    end else begin
`ifdef NLI_DEBUG
      $display("NLI:st mod_main_main=%d", cur_st);
      $display("NLI: r1_main =%d r3_main =%d r7_main =%d r6_main =%d r14_main =%d reg_t3_v1 =%d reg_t2_v3 =%d reg_t4_v4 =%d reg_t4_v5 =%d reg_t3_v6 =%d reg_t2_v9 =%d r6_main_v17 =%d r9_main_v18 =%d reg_t9 =%d reg_t10 =%d" ,r1_main ,r3_main ,r7_main ,r6_main ,r14_main ,reg_t3_v1 ,reg_t2_v3 ,reg_t4_v4 ,reg_t4_v5 ,reg_t3_v6 ,reg_t2_v9 ,r6_main_v17 ,r9_main_v18 ,reg_t9 ,reg_t10);
`endif
      // state output
      write_en_o <= (cur_st == `S_20);
      // FSM.
      case (cur_st)
        `S_0: begin
          addr_o <= 0;
          cur_st <= `S_65;
        end
        `S_65: begin
          r7_main <= o_insn_118_0;
          cur_st <= `S_3;
        end
        `S_3: begin
          r6_main_v17 <= wire_t13;
          if (wire_t13) begin
            cur_st <= `S_13;
          end else
          cur_st <= `S_63;
        end
        `S_13: begin
          reg_t2_v9 <= 32'd0;
          reg_t3_v6 <= 32'd1;
          reg_t4_v4 <= 32'd0;
          reg_t9 <= 2'd0;
          reg_t10 <= 2'd1;
          r6_main <= 2'd0;
          addr_o <= 1;
          cur_st <= `S_66;
        end
        `S_66: begin
          r9_main_v18 <= o_insn_121_0;
          cur_st <= `S_50;
        end
        `S_20: begin
          addr_o <= 2;
          data_o <= reg_t2_v3;
          cur_st <= `S_63;
        end
        `S_63: begin
          cur_st <= `S_63;
        end
        `S_50: begin
          reg_t3_v1 <= wire_t14;
          reg_t2_v3 <= wire_t15;
          r1_main <= wire_t16;
          r6_main <= wire_t17;
          if (wire_t17) begin
            cur_st <= `S_54;
          end else
          cur_st <= `S_20;
        end
        `S_54: begin
          r3_main <= reg_t3_v1;
          reg_t10 <= 2'd0;
          r6_main <= 2'd1;
          reg_t9 <= 2'd1;
          r14_main <= wire_t18;
          reg_t2_v9 <= wire_t18;
          reg_t4_v5 <= wire_t19;
          cur_st <= `S_50;
        end
      endcase
    end
  end

  // imported modules begin
  // imported modules end

  // sub modules begin
  // sub modules end

endmodule

module fib(clk, rst, addr_o, write_en_o, data_o, data_i);
  input clk;
  input rst;
  // EXTERNAL_RAM
  output [31:0] addr_o;
  output write_en_o;
  output [31:0] data_o;
  input [31:0] data_i;
  mod_main mod_main_inst(.clk(clk), .rst(rst), .addr_o(addr_o), .write_en_o(write_en_o), .data_o(data_o), .data_i(data_i));
endmodule

I wrote fib_test.v(test_bench for fib.v)

module fib_test;
   reg         clk = 0;
   reg         fib_rst;
   reg  [31:0] fib_mem[1:0];
   wire [31:0] fib_data_i;
   wire [31:0] fib_addr;
   wire        fib_wen;
   wire [31:0] fib_data_o;

   always #10
      clk <= !clk;

   task test;
      input [31:0] n;
      input [31:0] expected_result;
      integer      timeout;
      begin
         @(posedge clk);
         fib_mem[0] <= #1 1;
         fib_mem[1] <= #1 n;
         timeout    = 1000;
         begin: loop
            forever begin
               @(posedge clk);
               fib_mem[0] <= #1 0;
               if (fib_wen) begin
                  if (fib_data_o !== expected_result)
                      $display("fib_return = %d expected but %d found.", expected_result, fib_data_o);
          else
                      $display("fib_return = %d ok", fib_data_o);
                  disable loop;
               end
               if (timeout == 0) begin
                  $display("fib_wen is timeout.");
                  disable loop;
               end
               timeout = timeout - 1;
            end
         end
      end
   endtask

   initial begin
      fib_rst    <= 1;
      fib_mem[0] <= 0;
      fib_mem[1] <= 0;
      repeat(10) @(posedge clk);
      fib_rst    <= 0;
      repeat(10) @(posedge clk);
      test(0, 0);
      test(1, 1);
      test(2, 1);
      test(3, 2);
      test(4, 3);
      test(5, 5);
      test(6, 8);
      $stop;
   end

   assign fib_data_i = (fib_addr == 1) ? fib_mem[1] : fib_mem[0];

   fib dut(
       .clk       (clk       ),
       .rst       (fib_rst   ),
       .addr_o    (fib_addr  ),
       .write_en_o(fib_wen   ),
       .data_o    (fib_data_o),
       .data_i    (fib_data_i)
    );
endmodule // fib_test

simulation on Xilinx Vivado 2015.3

Vivado Simulator 2015.3
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2015.3/bin/unwrapped/win64.o/xelab.exe -wto ca0f9a24fe224f95b56a3f9bec2c8575 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot fib_test_behav xil_defaultlib.fib_test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "H:/gist/msgpack-vhdl-examples/examples/fibonacci/sim/vivado/neonlight/fib_test/fib_test.sim/sim_1/behav/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "H:/gist/msgpack-vhdl-examples/examples/fibonacci/sim/vivado/neonlight/fib_test/fib_test.sim/sim_1/behav/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.mod_main
Compiling module xil_defaultlib.fib
Compiling module xil_defaultlib.fib_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot fib_test_behav
Vivado Simulator 2015.3
Time resolution is 1 ps
run all
fib_wen is timeout.
fib_wen is timeout.
fib_wen is timeout.
fib_wen is timeout.
fib_wen is timeout.
fib_wen is timeout.
fib_wen is timeout.

Without becoming infinite loop , it seems they've been out of the loop at one time .
Do I make a mistake in anything?

Release v0.5.9

It will be in early July.

In Fibonacci program , simulation of the results does not match the expected value .

I wrote fib.n

object Fib = Kernel.clone();
object Global.Fib = Fib;

int Fib.param  = 0;
int Fib.result = 0;

def Fib.fib(){
  int curr;
  int next;
  int prev;
  int i;
  curr = 0;
  next = 1;
  for (i = 0; i < param; ++i) {
    prev = curr;
    curr = next;
    next = next + prev;
  }
  result = curr;
}
def Fib.main() {
   int *in  = 0;
   int *out = 1;
   param = *in;
   fib();
   *out = result;
}
if (Env.isMain()) {
  Fib.setDump("./tmp/fib");
  Fib.compile();
  Fib.writeHdl("fib.v");
  Fib.writeHdl("fib.cpp");
}

I generated fib.v use neon light compiler

shell% nli fib.n
print: default.n loaded
src/synth/synth.cpp:53:Synth start
output html file name=(./tmp/fib.0.raw.html)
output html file name=(./tmp/fib.1.expanded.html)
output html file name=(./tmp/fib.2.opt_pure_temp_variable_elimination.html)
output html file name=(./tmp/fib.3.opt_basic_block_shrink.html)
output html file name=(./tmp/fib.4.opt_ssa.html)
output html file name=(./tmp/fib.5.opt_ssa_assorted.html)
output html file name=(./tmp/fib.6.opt_ssa_cleanup.html)
output html file name=(./tmp/fib.7.opt_register_share.html)
output html file name=(./tmp/fib.8.opt_basic_block_shrink.html)
output html file name=(./tmp/fib.9.opt_resource_alloc.html)
output html file name=(./tmp/fib.10.optimized.html)
output html file name=(./tmp/fib.11.ll.html)
I:output file name=fib.v
I:output file name=fib.cpp

generated fib.v

// 0.1.9

module mod_main(clk, rst, addr_o, write_en_o, data_o, data_i);
  input clk;
  input rst;
  // EXTERNAL_RAM
  output [31:0] addr_o;
  output write_en_o;
  output [31:0] data_o;
  input [31:0] data_i;

  reg [31:0] addr_o;
  reg write_en_o;
  reg [31:0] data_o;

  reg [31:0]  r1_main;
  reg [31:0]  r3_main;
  reg  reg_t5;
  reg [31:0]  reg_t7;
  reg [31:0]  reg_t1_v1;
  reg [31:0]  reg_t3_v5;
  reg [31:0]  reg_t3_v6;
  reg [31:0]  r4_main_v11;
  reg [31:0]  reg_t1_v13;
  reg [31:0]  reg_t2_v14;
  reg [31:0]  reg_t3_v15;
  reg  reg_t8;
  reg  reg_t10;
  wire [31:0]  wire_t11;
  wire [31:0]  wire_t12;
  wire [31:0]  wire_t13;
  wire  wire_t14;
  wire [31:0]  wire_t15;
  wire [31:0]  wire_t16;

  // declare state begin
 `define S_0 0
 `define S_3 3
 `define S_57 57
 `define S_15 15
 `define S_43 43
 `define S_48 48
 `define S_54 54

  reg [6:0] cur_st;
  // declare state end

  // resources begin
  // branch_1


  // gt_6
  wire gt_6_d0;
  wire [31:0] gt_6_s0;
  wire [31:0] gt_6_s1;
  assign gt_6_s0 = (cur_st == `S_43) ? r4_main_v11 : (0);
  assign gt_6_s1 = (cur_st == `S_43) ? wire_t13 : (0);
  assign gt_6_d0 = (gt_6_s0 > gt_6_s1);

  // add_7
  wire [31:0] add_7_d0;
  wire [31:0] add_7_s0;
  wire [31:0] add_7_s1;
  assign add_7_s0 = (cur_st == `S_48) ? reg_t2_v14 : (0);
  assign add_7_s1 = (cur_st == `S_48) ? reg_t2_v14 : (0);
  assign add_7_d0 = (add_7_s0 + add_7_s1);

  // selector_10

  // sram_if_11

  // add_13
  wire [31:0] add_13_d0;
  wire [31:0] add_13_s0;
  wire [31:0] add_13_s1;
  assign add_13_s0 = (cur_st == `S_48) ? reg_t3_v15 : (0);
  assign add_13_s1 = (cur_st == `S_48) ? 32'd1 : (0);
  assign add_13_d0 = (add_13_s0 + add_13_s1);

  // resources end

  // insn wires begin
  assign o_insn_102_0 = data_i;
  wire [31:0] o_insn_103_0; // id:103
  assign o_insn_103_0 = data_i;
  wire [31:0] o_insn_95_0; // id:95
  assign o_insn_95_0 = reg_t8 ? r1_main : reg_t1_v1;
  wire [31:0] o_insn_98_0; // id:98
  assign o_insn_98_0 = reg_t5 ? reg_t7 : r3_main;
  wire [31:0] o_insn_101_0; // id:101
  assign o_insn_101_0 = reg_t10 ? reg_t3_v6 : reg_t3_v5;
  wire o_insn_67_0; // id:67
  assign o_insn_67_0 = gt_6_d0;
  wire [31:0] o_insn_74_0; // id:74
  assign o_insn_74_0 = add_7_d0;
  wire [31:0] o_insn_78_0; // id:78
  assign o_insn_78_0 = add_13_d0;
  assign o_insn_105_0 = data_i;
  // insn wires end

  // insn result wires begin
   assign wire_t11 = o_insn_95_0;
   assign wire_t12 = o_insn_98_0;
   assign wire_t13 = o_insn_101_0;
   assign wire_t14 = o_insn_67_0;
   assign wire_t15 = o_insn_74_0;
   assign wire_t16 = o_insn_78_0;
  // insn result wires end

  // sub state regs begin
  // sub state regs end
  always @(posedge clk) begin
    if (rst) begin
      cur_st <= `S_0;
    end else begin
`ifdef NLI_DEBUG
      $display("NLI:st mod_main_main=%d", cur_st);
      $display("NLI: r1_main =%d r3_main =%d reg_t5 =%d reg_t7 =%d reg_t1_v1 =%d reg_t3_v5 =%d reg_t3_v6 =%d r4_main_v11 =%d reg_t1_v13 =%d reg_t2_v14 =%d reg_t3_v15 =%d reg_t8 =%d reg_t10 =%d" ,r1_main ,r3_main ,reg_t5 ,reg_t7 ,reg_t1_v1 ,reg_t3_v5 ,reg_t3_v6 ,r4_main_v11 ,reg_t1_v13 ,reg_t2_v14 ,reg_t3_v15 ,reg_t8 ,reg_t10);
`endif
      // state output
      write_en_o <= (cur_st == `S_54);
      // FSM.
      case (cur_st)
        `S_0: begin
          r1_main <= 32'd0;
          reg_t7 <= 32'd1;
          reg_t3_v6 <= 32'd0;
          reg_t8 <= 2'd1;
          reg_t5 <= 2'd1;
          reg_t10 <= 2'd1;
          cur_st <= `S_3;
        end
        `S_3: begin
          addr_o <= 0;
          cur_st <= `S_57;
        end
        `S_57: begin
          r4_main_v11 <= o_insn_103_0;
          cur_st <= `S_43;
        end
        `S_15: begin
          cur_st <= `S_15;
        end
        `S_43: begin
          reg_t1_v13 <= wire_t11;
          reg_t2_v14 <= wire_t12;
          reg_t3_v15 <= wire_t13;
          reg_t5 <= wire_t14;
          if (wire_t14) begin
            cur_st <= `S_48;
          end else
          cur_st <= `S_54;
        end
        `S_48: begin
          reg_t1_v1 <= reg_t2_v14;
          reg_t8 <= 2'd0;
          reg_t5 <= 2'd0;
          reg_t10 <= 2'd0;
          r3_main <= wire_t15;
          reg_t7 <= wire_t15;
          reg_t3_v5 <= wire_t16;
          cur_st <= `S_43;
        end
        `S_54: begin
          addr_o <= 1;
          data_o <= reg_t1_v13;
          cur_st <= `S_15;
        end
      endcase
    end
  end

  // imported modules begin
  // imported modules end

  // sub modules begin
  // sub modules end

endmodule

module fib(clk, rst, addr_o, write_en_o, data_o, data_i);
  input clk;
  input rst;
  // EXTERNAL_RAM
  output [31:0] addr_o;
  output write_en_o;
  output [31:0] data_o;
  input [31:0] data_i;
  mod_main mod_main_inst(.clk(clk), .rst(rst), .addr_o(addr_o), .write_en_o(write_en_o), .data_o(data_o), .data_i(data_i));
endmodule

I wrote fib_test.v(test_bench for fib.v)

module fib_test;
   reg         clk = 0;
   reg         fib_rst;
   reg  [31:0] fib_data_i;
   wire [31:0] fib_addr;
   wire        fib_wen;
   wire [31:0] fib_data_o;

   always #10
      clk <= !clk;

   task test;
      input [31:0] n;
      input [31:0] expected_result;
      integer      timeout;
      begin
     fib_rst    <= #1 1;
         @(posedge clk);
         fib_data_i <= #1 n;
         fib_rst    <= #1 0;
         timeout    = 1000;
         begin: loop
            forever begin
               @(posedge clk);
               if (fib_wen) begin
                  if (fib_data_o !== expected_result)
                      $display("fib_return = %d expected but %d found.", expected_result, fib_data_o);
          else
                      $display("fib_return = %d ok", fib_data_o);
                  disable loop;
               end
               if (timeout == 0) begin
                  $display("fib_wen is timeout.");
                  disable loop;
               end
               timeout = timeout - 1;
            end
         end
      end
   endtask

   initial begin
      fib_rst    <= 1;
      fib_data_i <= 0;
      repeat(10) @(posedge clk);
      test(0, 0);
      test(1, 1);
      test(2, 1);
      test(3, 2);
      test(4, 3);
      test(5, 5);
      test(6, 8);
      $stop;
   end

   fib dut(
       .clk       (clk       ),
       .rst       (fib_rst   ),
       .addr_o    (fib_addr  ),
       .write_en_o(fib_wen   ),
       .data_o    (fib_data_o),
       .data_i    (fib_data_i)
    );
endmodule // fib_test

simulation on Xilinx Vivado 2015.3

Vivado Simulator 2015.3
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2015.3/bin/unwrapped/win64.o/xelab.exe -wto ca0f9a24fe224f95b56a3f9bec2c8575 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot fib_test_behav xil_defaultlib.fib_test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "H:/gist/msgpack-vhdl-examples/examples/fibonacci/sim/vivado/neonlight/fib_test/fib_test.sim/sim_1/behav/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "H:/gist/msgpack-vhdl-examples/examples/fibonacci/sim/vivado/neonlight/fib_test/fib_test.sim/sim_1/behav/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.mod_main
Compiling module xil_defaultlib.fib
Compiling module xil_defaultlib.fib_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot fib_test_behav
fib_return =          0 ok
fib_return =          1 ok
fib_return =          1 expected but          2 found.
fib_return =          2 expected but          4 found.
fib_return =          3 expected but          8 found.
fib_return =          5 expected but         16 found.
fib_return =          8 expected but         32 found.

don't match fib_return when (n>1)

Do I make a mistake in anything?

Release v0.5.7

Current plan is to release at the beginning of May.

This will include initial version of loop unrolling feature.

Release v0.5.6

Hopefully early April 2020.

It will include a feature to create read replicas of an array.

// Prepares 2 read replicas of array 'a'
@(num=2)
ram a int[16]

func f() (int) {
  // Reads from 0th and 1st replica which can happen concurrently.
  return a@0[0] + a@1[1]
}

Allow single binary installation

Snap packages are not so popular or useful on many environments namely WSL.

Introduce ticker object

Also deprecate getTickCount()

Ticker process interferes with other processes

Hi, I am running Ubuntu 20.04 with karuta-0.6.1 I do not know if this is a bug, but when I try to create a slow clock process as specified in the docs in the same file as another process, only the first one actually runs. E.g.

shared ticker object = Env.newTicker()
shared slowclk #0 = 0 

process slow_clk_proc() {
    ticker.decrementCount(ticker.getCount())
    print("slowclk enter")
    while true {
        print("slowclk always")
        wait(60 - ticker.getCount())
        ticker.decrementCount(60)
        slowclk = ~slowclk
    }   
}

process sd_card() {
    print("sdcard enter")
    while true {
        print("sdcard always")
    }   
}

will give me the following output when I run karuta run --duration 10 testclk.karuta

print: slowclk enter
print: sdcard enter
print: slowclk always
print: slowclk always
print: slowclk always
print: slowclk always
print: slowclk always

And if I swap the order:

shared ticker object = Env.newTicker()
shared slowclk #0 = 0 

process sd_card() {
    print("sdcard enter")
    while true {
        print("sdcard always")
    }   
}
 
process slow_clk_proc() {
    ticker.decrementCount(ticker.getCount())
    print("slowclk enter")
    while true {
        print("slowclk always")
        wait(60 - ticker.getCount())
        ticker.decrementCount(60)
        slowclk = ~slowclk
    }   
}

I get instead

print: sdcard enter
print: slowclk enter
print: sdcard always
print: sdcard always
print: sdcard always
print: sdcard always
print: sdcard always

My interval is 60 clocks so I tried different durations like 100 or 1000 but the pattern doesn't change.

Unable to access imported variables

#10
So in an attempt to solve the problem of a ticker process affecting other processes, I tried to move it out of the file. However, I am unable to access imported variables inside processes
E.g. slowclk.karuta:

shared slowclk #0 = 0

import.karuta:

import "slowclk.karuta" as sc

process main() {
    print(sc.slowclk)
}

Running karuta run --duration 10 import.karuta, I get the following error.

U:Failed to find object: sc
U:Failed in compilation of method: main
U:member not found: sc

Parallel hardware

Hi, first I would like to thank the developers for this new HLS tool, it looks very simple to use and seems to have a lot of potential, so I'm excited to use it.

I'm trying to write an FPGA-based accelerator for a project, but I'm not sure how to instantiate multiple instances of a function (in hardware). Not sure if I have this right but the for loops don't seem to be unrolled into hardware. Do you have an example of how to do this?

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