mrlution Goto Github PK

gallery

A Photo and Video Gallery Written in Flask

hadbadge2019_fpgasoc

FPGA SoC code and application example for Hackaday Supercon 2019 badge

image-classification-using-cnn-on-fpga

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

ituring_books

图灵程序设计丛书分享

motion-detection-system-based-on-background-reconstruction

This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.

mrlution.github.io

mstar_deeplearning_project

Radar target classification, detection and recognition using deeplearning methods on MSTAR dataset

nexys4ddr-arm-m3-plate-recognition

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

nutshell

RISC-V SoC designed by students in UCAS

opamp-generator

photoprism

Open-Source Photo Management powered by Go and Google TensorFlow

pipecnn

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

qqmessagemht2html

This is the python3 version of 404neko's mhtSpliter

rectilinearpackingproblemsolver

This repository contains the code to solve rectilinear packing problem

rest-auth

Example application for my RESTful Authentication with Flask article.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

rsyocto

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

sdm-dse

smartmpw

2020（第二届）集成电路EDA设计精英挑战赛，赛题三：智能 MPW 拼接

snake-fpga

A remastered SNAKE on the Altera DE1-SoC board. This project is implemented using Verilog HDL through Intel Quartus Prime. The youtube demo video will be up before the year 2100.

soc-based-on-m3

soundify

Soundify - Data transmission via sound waves

spio

A library of FPGA designs and re-usable modules for I/O and internal connectivity in SpiNNaker systems.

uestcbbs

刷河畔时间

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

verilogutilip

Here is a bunch of util IPs

vexriscvsoftcorecontest2018

vivado-library

webp2jpg-online

Use the browser's online image format converter, no need to upload files, you can convert jpeg, jpg, png, gif, webp, svg, ico, bmp files to jpeg, png, webp animation, gif, base64,avif,mozjpeg. 使用浏览器的在线图片格式转化器,无需上传文件,可将jpeg、jpg、png、gif、webp、svg、ico、bmp文件转换为jpeg、png、webp、webp动画、gif、base64、avif、mozjpeg,提供了多个可自定义选项来满足常见需求。

weightagnostic.github.io

repo for interactive article