A digital design of a five stage pipelined RISC processor.

• The data cache address space is 1 MB of 16-bit width and is word addressable. (Note: word = 2 bytes).
• There are eight 2-byte general purpose registers; R0, till R7.
• There are three special purpose registers
  • Program counter (PC).
  • Exception program counter (EPC).
  • Stack pointer (SP).
• The initial value of SP is (2^20-1).
• This project handles two types of exceptions
  • Empty Stack Exception which occurs when a pop is called while the stack is empty.
  • Invalid memory address which occurs when the address exceeds the range of 0xFF00.
• The exception handler address for empty stack exception is stored in the instruction cache in locations M[2] and M[3].
• The exception handler address for invalid mem address exception is stored in the instruction cache in locations M[4] and M[5].
• When an exception occurs, the address of the instruction causing the exception is saved in the exception program counter (EPC).
• There are 3 flags; implemented in a condition code register named flags<3:0>
  • Zero flag, flags<0>, which changes after arithmetic, logical, or shift operations.
  • Negative flag, flags<1>, which changes after arithmetic, logical, or shift operations
  • Carry flag, flags<2>, which changes after arithmetic or shift operations.
• There is one input port named that takes a value from the port and write it in a register.
• There is one output port that takes a value from a register and out it to the port.
• There is a Reset signal named reset in the integration.vhd