mohitkumarahuja / 2d-filtering-using-vhdl Goto Github PK

The goal is to process the input data flow (corresponding to lena image) using a 2D filter. Two main tasks are expected:  The design and the validation of a customizable 2D filter (filter IP)  The implementation on a Nexys4 evaluation board of the 2D filter. The filter IP implementation should be included in a reference design (furnished by teacher) to ease the integration. The filter IP could be split into two main parts: the memory cache which aims to be temporarily stored the data flow before filtering and the processing part. The cache memory designed for simultaneous pixel accesses enables a 3x3 pixel neighbourhood to be accessible in one clock cycle. The structure is based on flip-flop registers and First-In-First-Out (FIFO) memory.