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This project forked from rdilip/fpga
FPGA resources Ettus
Makefile 0.24%
Verilog 94.63%
Python 0.15%
PHP 0.02%
Shell 0.51%
SystemVerilog 1.05%
Batchfile 0.27%
Coq 0.38%
Tcl 0.64%
VHDL 1.16%
HTML 0.61%
Stata 0.27%
C 0.04%
C++ 0.01%
SourcePawn 0.02%
JavaScript 0.01%
Perl 6 0.01%
fpga's Introduction
- Frontend / Backend: ReactJS / Node.js(Express), Python (Django, Flask, aiohttp, and starlette)
- Database / API: Postgres, MySQL, MongoDB / REST, GraphQL, gRPC
- EDA / FPGA: Altium Designer / Xilinx Vivado & Vitis, Implement digital signal processing (DSP) algorithms on FPGAs
- SDR Platforms: GNURadio, USRP Hardware Driver (UHD), MATLAB and LabVIEW
- Languages: Verilog/VHDL, C/C++, Bash/Shell, Go, Rust, Python, JavaScript (TypeScript) and Node.js
- Additional Skills: Agile Project Management, Test-driven development, Microservices architecture, AWS, CI/CD tools
- ๐ฑ currently exploring Python AsyncIO, Vitis AI; and trying to build some projects using TensorFlow, TensorFlow2, and Pytorch framework.
- ๐ญ playing with Rust, WebAssembly, and Web3 stuff; interested in most fields, ping me if you want to collaborate.
fpga's People
Contributors