mfkiwl / q-engine Goto Github PK

Engine that Q

• RISCV processor core with memory and peripheral
• Xbaseband instruction extension plugin to control vector processor
• Vector processor organizes parallel memory access.
• Reconfigurable Data Path main DSP computational unit.
• Input / Output streaming DMA controllers
• DDR Memory controller and DMA

• 5 stage pipeline RISCV RV32I core
• no cache
• VexRsicv framework
• custom instruction extensions to control vector processor

Array of identical slices controlled by the same Xbaseband instruction. Each slice contains memory bank, can manage multiple memory pointers, and organize data traffic between vector memory and the datapath.

For more details see: https://github.com/siglabsoss/riscv-baseband

The Reconfigurable Data Path (datapath) sub-module is the major computational part of the Q-engine. Most of complex arithmetic DSP operations performed by the units of the datapath. Vector processor push input data into the datapath and pull computed results out of the datapath. Specific datapath structure can be changed by Vector processor to perform different computational algorithms.

For more details see: https://github.com/siglabsoss/datapath

• tightly coupled memory blocks
  • Instruction SRAM memory (iMEM) 8KiB
  • Data SRAM memory (dMEM) 1KiB
• Control bus (APB) to program DMA block CSRs
• Interrupt controller

• Each DMA have control bus (APB) and data bus (AXI) connection.
• End-Point DMA (connected to ADC / DAC) will have highest priority.
• Each DMA may trigger RISCV interrupt
• queue of descriptors

• Takes start address and vector length from CSR
• Pull data from streaming interface
• Writes data to the Vector Memory sequentially
• Sends interrupt when done

• Takes start address and vector length from CSR
• Reads data from the Vector Memory sequentially
• Pushes into streaming interface
• Sends interrupt when done

• Takes descriptor from CSR
  • start read address
  • start write address
  • vector length
• Reads data from one memory
• Writes data to the other memory
• Sends interrupt when done

*Arbitrates memory accesses for multiple dmas or memory read/write peripherals *Routes read data stream to the appropriate channel

Oh, you'd like me to connect the dots for you, lead you from A to B to C, so that your puny mind could comprehend? How boring.