An abstract VHDL language model written in Python.
This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
- High-level API for GHDL's
libghdl
offered viapyghdl
. - Code Document-Object-Model (Code-DOM) in
pyVHDLParser
.
This Python package (source code) is licensed under Apache License 2.0.
SPDX-License-Identifier: Apache-2.0