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View Code? Open in Web Editor NEW100 Days of CHISEL inspired by 100DaysOfRTL
100 Days of CHISEL inspired by 100DaysOfRTL
@hamnamohi please add tutorials for more wire constructs like WireInit.
Following Topics need to be added in the mentioned day wise order.
See CONTRIBUTING.md to see contributor guide.
Day-wise Topics
Day | Topic |
---|---|
Day 21 | Up down counter |
Day 22 | Mux_Tree |
Day 23 | Mux_2to1 |
Day 24 | Mux Case |
Day 25 | Mux Lookup |
Day 26 | Basic Branch Control |
Day 27 | Basic Immediate extension |
Day 28 | Black Box Adder |
Day 29 | Arbiter Queue |
Day 30 | Finite State Machine |
Day 31 | FSM for decoding Manchester encoding |
Day 32 | FSM Up down Counter |
Day 33 | UART Transmitter |
Day 34 | Detect Sequence |
Day 35 | Priority Arbiter |
Day 36 | Round Robin Arbiter |
Day 37 | Masked Read Write |
Day 38 | Forwarding for 2-banked memory |
Day 39 | Instruction steam |
Day 40 | Memory bank accessed by an arbiter |
Day 41 | Asynchronous memory |
Day 42 | Synchronous memory |
Day 43 | Parameterized memory |
Day 44 | Single Cycle ALU Design |
Day 45 | ALU Operations and Flags |
Day 46 | Register File Design |
Day 47 | Data Memory Unit |
Day 48 | Instruction Memory Unit |
Day 49 | Control Unit Design |
Day 50 | Single Cycle CPU Integration |
Day 51 | Basic IO Interface |
Day 52 | Testing the Single Cycle CPU |
Day 53 | Single Cycle CPU Performance Metrics |
@5hayanB update readme for day 9 10 and 11.
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