IC Design Project in Verilog for finding the maximum number in a sequence of 20 input numbers. Design stages:

1. Writing the Verilog library of the basic gates;
2. Writing the Verilog behavioral model of the circuit using the library of the basic gates;
3. Functional testing of the behavioral model by the ModelSim;
4. Synthesizing the behavioral model by the Yosys software and testing the synthesized model by the ModelSim;
5. Writing the SDF file for the timing delays of the basic gates;
6. Making a timing simulation of the whole circuit;
7. Importing the circuit into the Electric VLSI and placing and routing the cells;
8. Making a clock routing minimizing clock skew;
9. Making an EDIFF file of the circuit.