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A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools

VHDL 77.55% Tcl 1.11% Batchfile 1.15% Shell 1.82% PureBasic 8.32% C 8.40% Makefile 0.61% C++ 1.05%

designing-a-custom-axi-slave-peripheral's Introduction

Designing a Custom AXI Slave Peripheral

A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools

This is an application note for users wishing to design their own AXI4-lite slave peripherals in Xilinx embedded processor systems.

This version of the application note was written for the Xilinx Zynq-7000 devices, using the Avnet ZedBoard. This information is equally applicable to other Xilinx boards and architectures where the AXI4 interconnect is used.

The provided example code was written for the Xilinx Vivado tools.

Contributions

Code examples are provided for your use, but please feel free to contribute your own code back to this repository via a pull request in the usual fashion. Please fork from this repo, then create a suitably named branch in your fork before submitting back to this repo. Please don't submit a pull request from your "master" branch. Each new addition to the code should belong to its own submitted branch. Thanks.

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