Comments (3)
Thanks, I'll take a closer look.
from r68k.
Hi,
This code uses the QuickCheck crate from here https://github.com/BurntSushi/quickcheck and bunch of the code to set up the tests can be found here https://github.com/marhel/r68k/blob/master/emu/src/musashi.rs#L565
from r68k.
Yes, there's no separate sources for that, this kind of testing is done by loading the Musashi lib into the process, and interacting with it via Rusts C-interop. Then the test cases uses QuickCheck to come up with a random configuration of registers, status flags and memory, and we try our best to set up both Musashi and r68k cores this way, and then run a single instruction, and compare the effects on both cores afterwards.
The code uses Rust macros heavily, such as;
qc!(MASK_OUT_Y, OP_CMPI_32_PD, qc_cmpi_32_pd);
This macro generate a test function called qc_cmpi_32_pd, to test a particular variation of the CMP instruction (32-bit immediate value with address register postdecrement). The mask MASK_OUT_Y, tells us which bits in the opcode can vary (in this case, the 'Y' register part may vary, which controls which address register is used), because we loop to cover all opcode variants explicitly instead of relying on randomization to hit all opcode variations.
Then we also run completeness tests that runs through all 64K possible opcodes, (1K per test) such as:
qc_allow_exception!(BLOCK_MASK, BLOCK_7K, qc_block7k);
Which does the same thing. The reason we differentiate between these cases, and don't randomize the exact opcode, are that during initial development with just a few opcodes implemented, it's not helpful to know that the cores differ when asked to execute, say, opcode 0x4313 with some values, because you'd need a disassembler to know which operation that was.
Much more helpful when implementing CMP, to see that the instruction effects appears to differ when using A7 postdecrement, say, or (an actual case) ADDA differs when the same register is used as both source and destination
from r68k.
Related Issues (20)
- Implement TRAPV HOT 1
- Implement TST HOT 1
- Implement UNLK HOT 1
- Diff MAME version of Musashi with current HOT 29
- Compiler gets stuck when building release HOT 17
- Use default for Cpu struct
- More accurate cycle emulation for DIVS/DIVU needed?
- CHK, DIVU, DIVS trap case cycles differs from Musashi HOT 6
- Streamline qc and op_handler macros HOT 1
- Improve performance during QC HOT 27
- Improve QC coverage HOT 8
- Use a logging framework HOT 1
- Disassembler HOT 27
- Implement opcode completeness test HOT 5
- Consider using a codegen for glue HOT 2
- Generating cycle tables HOT 23
- Turn r68k into a lib HOT 14
- Host callbacks HOT 11
- fuzix HOT 2
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from r68k.