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Skywater 130nm Klayout Device Generators PDK

License: GNU Affero General Public License v3.0

Python 57.59% Makefile 23.80% Shell 18.61%

pdk skywaters pcells analog-layout custom-layout chip-design

sky130_klayout_pdk's Introduction

Skywater 130nm Technology PDK for KLayout

Mabrains is excited to share with you our Skywater 130nm PDK for Klayout. These files are not qualified. Please use with caution.

KLayout technology files for Skywater Sky130

sky130.lyt : technology and connections description
sky130.lyp : layers color and shape description
DRC : please use the following --> https://github.com/efabless/mpw_precheck/blob/main/checks/tech-files/sky130A_mr.drc
LVS : LVS script lvs/lvs_sky130.lylvs (In development)
Pcells : Devices generators (In development)

Installation

To use this repo, you need to do the following:

Clone the repo:

git clone <https://github.com/mabrains/sky130_klayout_pdk.git>

Go inside sky130_klayout_pdk:
```
cd sky130_klayout_pdk
```
Open klayout using the following command:
```
KLAYOUT_HOME=./sky130_tech klayout -e
```

Status

Devices Status

Device Name	Model	Status	DRC	LVS	Number of Cases	Method of verification
Nmos 1.8v	sky130_fd_pr__nfet_01v8	✔️	✔️	✔️	163	Semi automated
pmos 1.8v	sky130_fd_pr__pfet_01v8	✔️	✔️	✔️	163	Semiautomated
nmos 5v	sky130_fd_pr__nfet_g5v0d10v5	✔️	✔️	✔️	90	Semi automated
pmos 5v	sky130_fd_pr__pfet_g5v0d10v5	✔️	✔️	✔️	90	Semi automated
mimcap_1	sky130_fd_pr__model__cap_mim	✔️	✔️	✔️	122	Semi automated
mimcap_2	sky130_fd_pr__cap_mim_m4	✔️	✔️	✔️	122	Semi automated
npn	sky130_fd_pr__npn_05v5	✔️	✔️	✔️	2	Semi automated
pnp	sky130_fd_pr__pnp_05v5	✔️	✔️	✔️	2	Semi automated
P- poly_res	sky130_fd_pr__res_xhigh_po	✔️	✔️	not_perfect	113	Semi automated
via_generator	Connectivity	✔️	✔️	Connectivity	10	Manual
Single_inductor	Mabrains Device	✔️	not perfect	No LVS Available	5	Manual
rectangular_shielding	Mabrains Device	✔️	not perfect	No LVS Available	5	Manual
diff_octagon_inductor	Mabrains Device	✔️	not perfect	No LVS Available	5	Manual
diff_square_inductor	Mabrains Device	✔️	not perfect	No LVS Available	5	Manual
n-diode	sky130_fd_pr__diode_pw2nd_,sky130_fd_pr__model__parasitic_	❌	❌	❌	❌	❌
p-diode	ky130_fd_pr__diode_pd2nw_*	❌	❌	❌	❌	❌
nmos 1.8 lvt	sky130_fd_pr__nfet_01v8_lvt	❌	❌	❌	❌	❌
diff-resistor		❌	❌	❌	❌	❌
mom cap	sky130_fd_pr__cap_vpp_*	❌	❌	❌	❌	❌
NMOS ESD FET	sky130_fd_pr__esd_nfet_[01v8,g5v0d10v5,g5v0d10v5_nvt]	❌	❌	❌	❌	❌
11V/16V NMOS FET	sky130_fd_pr__nfet_g5v0d16v0	❌	❌	❌	❌	❌
3.0V native NMOS FET	sky130_fd_pr__nfet_03v3_nvt	❌	❌	❌	❌	❌
5.0V native NMOS FET	sky130_fd_pr__nfet_05v0_nvt	❌	❌	❌	❌	❌
20V NMOS FET	sky130_fd_pr__nfet_20v0	❌	❌	❌	❌	❌
20V isolated NMOS FET	sky130_fd_pr__nfet_20v0_iso	❌	❌	❌	❌	❌
20V native NMOS FET	sky130_fd_pr__nfet_20v0_nvt	❌	❌	❌	❌	❌
20V NMOS zero-VT FET	sky130_fd_pr__nfet_20v0_zvt	❌	❌	❌	❌	❌
20V NMOS zero-VT FET	sky130_fd_pr__nfet_20v0_zvt	❌	❌	❌	❌	❌
10V/16V PMOS FET	sky130_fd_pr__pfet_g5v0d16v0	❌	❌	❌	❌	❌
1.8V high-VT PMOS FET	sky130_fd_pr__pfet_01v8_hvt	❌	❌	❌	❌	❌
1.8V low-VT PMOS FET	sky130_fd_pr__pfet_01v8_lvt	❌	❌	❌	❌	❌
20V PMOS FET	sky130_fd_pr__pfet_20v0	❌	❌	❌	❌	❌
P+ poly_res	sky130_fd_pr__res_high_po	❌	❌	❌	❌	❌
N-pass FET (SRAM)	sky130_fd_pr__special_nfet_pass	❌	❌	❌	❌	❌
N-latch FET (SRAM)	sky130_fd_pr__special_nfet_latch	❌	❌	❌	❌	❌
P-latch FET (SRAM)	sky130_fd_pr__special_pfet_pass	❌	❌	❌	❌	❌
Varactors	sky130_fd_pr__cap_var_lvt , sky130_fd_pr__cap_var_hvt	❌	❌	❌	❌	❌

sky130_klayout_pdk's People

Contributors

Stargazers

Watchers

Forkers

loesterfranco britovski rpg-7 pepijndevos joamatab taherkourany leochand101 ahmedalshahat vlsida yongjun-zhao

sky130_klayout_pdk's Issues

DRC issue

Hi ,

Trying to use a VIA - metal1 metal2 VIA. But Seems following DRC exists.

m2.5 [via_new]
m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um
polygon: (0.425,-0.395;0.425,-0.245;0.575,-0.245;0.575,-0.395)

Thanks

PINs

How can we add pins so we can recognize the ports of the device?

Ideas for improvement

Simplify Pcells. How could we simplify the Pcells code by adding different levels of hierarchy? For example, Pcells could be greatly simplified
how can we make them available through PyPi and Klayout package manager? We could add them as PRs to this repo, which has both
Write tests and documentation
add ports so we can route and connect different PCells

Parasitic Extraction Support Needed

Our Magical team is currently working on supporting skywater-pdk to enable open-sourced tape out design. We have already finished the PMOS and NMOS device generation part, and are in desperate need of your support for the resistor and capacity LVS file to further boost the impact of both your open-sourced skywater-pdk and our Magical tool. Could you provide the resistor and capacitor LVS file? We also need parasitic extraction to generate the analog IC layout automatically.

Thanks for your help.

`ERROR: invalid literal for int() with base 10: 'Connection Up' in PCellDeclaration.produce`

KLayout version 0.27.8 (fresh install)
Sky130 PDK 9d36065
Python 3.8.10
Linux 5.13.0-30-generic #33~20.04.1-Ubuntu SMP Mon Feb 7 14:25:10 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux

Trying to place a nmos, I get the following error (and nothing happens):

ERROR: invalid literal for int() with base 10: 'Connection Up' in PCellDeclaration.produce
  /home/llandsmeer/.klayout/tech/sky130/pymacros/sky130_pcells/nmos18.py:123
  :/built-in-pymacros/pcell_declaration_helper.lym:185

gds in your test cases

@mohanad0mohamed Hello, Is it possible to let me know where did you find the gds files that you have here? I can't find these in the Skywater repository.

sky130.lylvs: XML parser error

Root cause

Angle brackets in copyright comment result in XML parser error:

> ...
> # You should have received a copy of the GNU Affero General Public License
> # along with this program.  If not, see <https://www.gnu.org/licenses/>.

Actual Behavior

ERROR: Reading .../klayout_sky130/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49

Steps to Reproduce the Problem

Run:
> KLAYOUT_HOME=./sky130_tech klayout -e

Specifications

Version: Latest
Platform: Ubuntu 22.04.1 LTS

LVS support for devices

Hi. Your repo mentions that for most of the devices are verified by "semi-automatic". Does that include automated LVS scripts that extract resistor/capacitor devices? It seems that I am unable to find how res/cap are extracted in your LVS script: https://github.com/mabrains/sky130_klayout_pdk/blob/main/lvs/lvs_sky130.lylvs

Thanks for the help.

ERROR: sky130.lym:9: No module named 'cells'

Platform

Ubuntu 22.04
Klayout 0.28.5
sky_130_klayout_pdk latest from git

Steps to Reproduce the Problem

Run

KLAYOUT_HOME=./sky130_tech/ klayout -e

The following error messages are shown in terminal

ERROR: Reading /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49
ERROR: Reading /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49
ERROR: /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/pymacros/sky130.lym:9: No module named 'cells'
  /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/pymacros/sky130.lym:9 (class ModuleNotFoundError)

The first two are related to #28. But what is the No module cells error?

mabrains / sky130_klayout_pdk Goto Github PK

sky130_klayout_pdk's Introduction

Skywater 130nm Technology PDK for KLayout

KLayout technology files for Skywater Sky130

Installation

Status

Devices Status

sky130_klayout_pdk's People

Contributors

Stargazers

Watchers

Forkers

sky130_klayout_pdk's Issues

Root cause

Actual Behavior

Steps to Reproduce the Problem

Specifications

Platform

Steps to Reproduce the Problem

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