I have tried to use the following example code:

from nmigen import *

from nmigen_boards.de10_lite import *

from nmigen.build import *
from nmigen.vendor.intel import *
from nmigen_boards.upduino_v2 import *

class Blinky(Elaboratable):
    def elaborate(self, platform):
        led   = platform.request("led", 0)
        timer = Signal(20)

        m = Module()
        m.d.sync += timer.eq(timer + 1)
        m.d.comb += led.o.eq(timer[-1])
        return m


if __name__ == "__main__":
    platform = DE10LitePlatform()
    platform.build(Blinky(), do_program=True)

But I get this error:

Traceback (most recent call last):
  File "/run/media/sci4me/ldata/Projects/nmigen-test/test.py", line 22, in <module>
    platform.build(Blinky(), do_program=True)
  File "/usr/lib/python3.9/site-packages/nmigen/build/plat.py", line 78, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/usr/lib/python3.9/site-packages/nmigen/build/plat.py", line 120, in prepare
    fragment._propagate_domains(self.create_missing_domain, platform=self)
  File "/usr/lib/python3.9/site-packages/nmigen/hdl/ir.py", line 380, in _propagate_domains
    new_domains = self._create_missing_domains(missing_domain, platform=platform)
  File "/usr/lib/python3.9/site-packages/nmigen/hdl/ir.py", line 356, in _create_missing_domains
    value = missing_domain(domain_name)
  File "/usr/lib/python3.9/site-packages/nmigen/build/plat.py", line 102, in create_missing_domain
    clk_i = self.request(self.default_clk).i
  File "/usr/lib/python3.9/site-packages/nmigen/build/res.py", line 62, in request
    resource = self.lookup(name, number)
  File "/usr/lib/python3.9/site-packages/nmigen/build/res.py", line 57, in lookup
    raise ResourceError("Resource {}#{} does not exist"
nmigen.build.res.ResourceError: Resource clk50#0 does not exist

Switching to DE-10 Nano, for example, does not have this problem and works just fine.

Boards using it:

• versa_ecp5, versa_ecp5_5g

I try to implement a board file for the colorlight 5a-75b v7.0.
According to the Litex migen file the SPI clock is not driven by the FPGA.

When I try to instantiate SPIFlashResources without the clk parameter, I get TypeError: SPIFlashResources() missing 1 required keyword-only argument: 'clk'

Should I set it to P6 also?

Boards using it:

• versa_ecp5, versa_ecp5_5g

Boards using it:

• versa_ecp5, versa_ecp5_5g

This was added in m-labs/nmigen@367ad5a and could be used to make resources more flexible.

Boards using it:

• blackice, blackice_ii

Occasionally, it is possible a user will want to add their custom Resource to their boards Connectors that matches the following conditions:

• A Subsignal of their shiny new Resource has multiple Pins that should be associated with it.
• The Pins of this Subsignal will be spread out across multiple Connectors.

omigen already handles this case by hardcoding the connector to use into the Pins string, as per this example on the b Subsignal.

What should the equivalent nmigen behavior be?

My Proposal

vga = [
        ("vga_out", 0,
            Subsignal("hsync", PinsN("3", dir="o", conn=("led", 0))),
            Subsignal("vsync", PinsN("4", dir="o", conn=("led", 0))),

            Subsignal("r", Pins("1 2 3", dir="o", conn=("dio", 0))),
            Subsignal("g", Pins("4 5 6", dir="o", conn=("dio", 0))),
            Subsignal("b", Pins("7", dir="o", conn=("dio", 0)),
                           Pins("1", dir="o", conn=("clkio", 0))),
            Attrs(IOSTANDARD="LVCMOS33", SLEW="FAST")
        )
    ]

Primarily because defining many of them in sequence is tedious, annoying and error-prone. NB: non-sequential resource numbers should be handled well.

Differences between various 7SDs:

• Common cathode vs anode?
• Is decimal point used?
• Are the digit enable signals one-hot coming out of the FPGA or not?
  • Using a single enable line, where 0 controls one digit, and 1 controls the other seems more
    common when only two digits are present (fairly common setup). Otherwise, one-hot is used.

Potential Subsignal naming scheme:

• a, b, ... g, dp for decimal point (if present)
• en{0, 1, 2}
  • How should one-hot vs shared en be handled in naming. Should there be a difference?

Boards using it right now

None! But Mercury will (for the baseboard peripheral that is normally attached to it), and in omigen, the naming scheme was inconsistent. So I want to fix this before it becomes a problem.

It's very important to have an easily available litmus check for a correctly installed and configured toolchain for any particular board. I propose that any board that is run as __main__ should demonstrate that by running a blinky. (Are there any boards without LEDs and what can we do about it?)

This is currently done and tested for:

• icestick
• ice40_hx1k_blink_evn
• tinyfpga_bx

Now that m-labs/nmigen#128 and m-labs/nmigen#129 are merged, board files may be improved.