A simulated memory controller for use in FPGA designs that want to model real system performance.

This project has been developed in the Google Summer of Code 2020 for LowRisc CIC, supervised by Greg Chadwick, Pirmin Vogel and Alex Bradbury.

Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

The simulated memory controller has two AXI ports (one slave and one master) dedicated to its integration between the requester (typically the CPU core) and the real memory controller.

Two testbenches are integrated in the repository:

• A testbench for the whole simulated memory controller, which is discussed here.
• A testbench for the response banks, as it is a relatively complex design block.

See the documentation for more information about the testbenches.

The required tools are Verilator and FuseSoC. Additionally, GTKWave is used for analyzing waveforms.

To run the complete testbench,

Step 1: Clone the repository and move to the repository root:

git clone https://github.com/lowRISC/gsoc-sim-mem.git simmem
cd simmem

Step 2: Initialize FuseSoC and add the simmem core:

fusesoc init
fusesoc library add simmem .

The main testbench checks the functionality and performance of the simulated memory controller by:

• Checking the write response ordering according to the corresponding requests.
• Displaying the actual delays.

Step 1: To compile the design and testbench, execute:

fusesoc run --target=sim_simmem_top simmem

Step 2: To generate the waveforms, execute:

./build/simmem_0.1/sim_simmem_top-verilator/Vsimmem_top --trace

This runs the testbench again, but this time it generates the top.fst wave file. The testbench standard output is described in the documentation.

Step 3: To view the waveforms, execute:

gtkwave top.fst

This opens the waveform GUI for a deeper analysis.