Elaborate chisel type annotation from firtool to generate debug information for the Tywaves project about circt HOT 2 OPEN

I think we can to expose the chisel type via compiler plugin like what we did in the source info. But what on earth is a chisel type? That’s the fundamental question(we need specification)

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I think we can to expose the chisel type via compiler plugin like what we did in the source info.

I already managed to expose source level information from chisel to firrtl and firtool. In the meantime I also managed to read this information from firtool, processing it into proper debug variables and updating hgldd/emitting a new file format.

But what on earth is a chisel type? That’s the fundamental question(we need specification)

Whit chisel type refer to the type of the scala variable in the source chisel code.
In the following example:

class MyBundle(size: Int) extends Bundle {
   val a = Bool()
   val b = SInt(size.W)
   val nested = new Bundle {
      val x = UInt(8.W)
   }
}
val inBundle  = IO(Input(new MyBundle(10)))
val wireBundle = Wire(new MyBundle(7))
val outBundle = IO(Output(new MyBundle(9)))) 

The types would be

Namely, I refer to anything represented in this table, including user-defined types:
https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/type_hierarchy.svg?sanitize=true
This is basically the information I'm trying to emit in a file format similar to hgldd: chipsalliance/chisel#4015 (comment)

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