Implement lowerings from various FIRRTL nodes to rtl.concat about circt HOT 7 CLOSED

@drom is looking into this

from circt.

About firrtl.shl(x, 4) ==> {x, 4'h0} convertion

FIRRTL

Has two kinds of shift operations:

Static:

Dynamic:

VerilogRTL

Has shift operators:

• logical shift operators, << and >>
• arithmetic shift operators, <<< and >>>

Should we have them in the RTL Dialect?

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About firrtl.cvt

FIRRTL

Verilog RTL

Should we have $signed operation type in RTL Dialect?

from circt.

Yeah, it is a good question about whether we have signed or unsigned types in RTL dialect. It doesn't really make sense for a hardware oriented dialect to do that, but given the importance of Verilog in practice, it might make sense.

For now, lets stick with signless types. If it becomes a problem in practice we can always revise this.

from circt.

Also xref for general background (not saying this is the right thing to do here necessarily): https://mlir.llvm.org/docs/Rationale/Rationale/#integer-signedness-semantics

from circt.

Vivado HLS uses LLVM-style signless types for most of the compiler. This causes some subtleties in range analysis which tracks a signed range and an unsigned range for each value. In RTL, signed operations are typically represented like:

wire [8:0] add_ln235_fu_662_p2;
reg [8:0] j_0_reg_360;
assign add_ln235_1_fu_687_p2 = ($signed(9'd482) + $signed(j_0_reg_360));

(In other words, most everything is declared as vectors of bits and signed operations are expressed by always converting the operands to signed. There are a few places where wires are declared as signed, but this is the exception more than the rule.)

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I think this is complete now!

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