How to build a Bit Matched, Resource Precise, and Clock Cycle Accurate C Model for an ASIC / IC circuit module? Example: Moving Mean of 32 point of input stream.
Author : Lin Junyang Version : 01 All rights reserved.
This project teach you to build a Bit Matched, Resource Precise, and Clock Cycle Accurate C Model for an ASIC / IC circuit module. Challenges:
- Change the 32 points moving mean to 64 points mean.
- Build you RTL (Verilog or VHDL) of the module, and verify it with the C Module.