liuyh-horizon / axi-multidma-ultra96v2 Goto Github PK
View Code? Open in Web Editor NEWSimple Project for Beginners of Ultra96 V2: Implement a simple Verilog project to transmit an 32-bits integer array from PS to PL in four DMAs. PL computes the sum of received data and transmits the result back to PS based on AXI-DMA.
License: MIT License