Konkuk Univ. junior, Embedded Computing class - Park Jonghyuk, Ko Ryeowook
Designing a controller for memory-based FFT Accelerator using Verilog HDL
- Block diagram of the FFT Acclerator
- Code provided (Verilog HDL)
- axis_fft.v, BF.v, FFT.v, FFTcore.v, MULT.v, TopFFT.v
- Code provided (C)
- Reference SDK program
- except "fft_hw" function in main.c, in which flushes and activates DMA.
- Timing diagram of the whole set
- More details : TP_EC22_r3.pdf
- Output result accuracy compared to reference output
- Considered the input, output, and AXI handshake(valid, ready)
- Considered whether it is possible to synthesize
- 50MHz clock reference, considered the worst negative slack
- Verilog HDL, C
- Vivado 2017.4, Vivado SDK
- Zybo Z7-20
- controller_16pt_2.v, controller_64pt.v
- sdk_src main.c "fft_hw" function
- More details : TP_EC2022_16pt_5조.pdf, TP_EC2022_64pt_5조.pdf
- Accuracy (NSR) and speed compared to reference(only using SW) were evaluation criteria.
- Comparison between implementing FFT through HW(using DMA) and implementing only through SW(reference)
- More details : TP_EC2022_16pt_5조.pdf, TP_EC2022_64pt_5조.pdf
- Improved my Verilog HDL and C language skills
- Synthesis-able Verilog code
- Understanding of AXI handshake
- Be skillful of Vivado, Vivado SDK SW tools
- Vivado, SDK settings
- Simulation (Behavioral, Synthesis, Implementation)
- Timing Summary (setup/hold time, worst negative slack)
- Hardware debugging (ILA wave)
- Creating IP project
- Understanding of Vivado block design (AXI interconnect, DMA, ZYNQ7 processing system), port connecting
- Understanding of Computer Architecture
- DMA, AMBA AXI protocol
- Understanding of FFT