UTFT board up-converter dies when powered without LED connected.
To resolve the issue, the next iteration should include 30V zener to limit output voltage in no-load situation.
Hand soldering thermal profile is too high >200C. There is need to use automated oven with 160C-170C MAX in profile to avoid scorching of white plastic 40P component.
Up-converter inductor is too close to board's edge. Same with capacitors.This makes the panel hole cutting dimensions unnecessarily too accurate. All needs to be moved 3-5 mm closer to center of the board. Also large 40P connector is too close to the edge.
Inductor pads on digital board should be larger for more solder. Or may be preheating needs to be longer for inductor to heat up for better solder wetting
This "LOW PRIORITY issue"
Study, how come the board has survived inverted DC power polarity mistake.
The DC was 5V limited to 160mA. The duration was about 0.5 sec.
Look at schematics and see what and why allowed the board to sirvive
Software clocking details for UTFT, fuses changes for Atmel, voltage 3.4V must be documented.
Fuses are programmed differently to Arduino Mega R3
Main UTFT library has no example for 8MHz clocking - add it.
External clocking for SSD1963 has special requirement for wiring of unused inputs - note it.
Voltage 3.4V is a compromise - a highest acceptable voltage by Solomon chip and potentially lowest acceptable voltage for Atmel chip when unofficially overclocked from 8MHz to 10-12-16MHz (in future).
Consumed current is 150 mA with local up-converter running
Consumed current is 30-40 mA with local up-converter not running
OK symptom: Consumed current is ~120 mA with local up-converter running and when Atmel chip is not programmed.
FAULT symptom: Consumed current is 130-140 mA with local up-converter running and when Solomon chip is miswired.
FAULT symptom: Consumed power is >200mA and LM regulators are hot, when there are shorting bridges.
Add white block area to silk screen to mark the manufacturing date and serial numbers by hand.
Establish dates labels (week / year), serial numbering and online journaling for future stats about faults, components supplier batches, soldering profiles, supplementary materials, packing materials
Attempt to trace climatic conditions / elevation (barometric) / temperature / humidity / winter freezing cycles for potential faults caused by ROHS materials ("tin whiskers") over next 5 years
Attempt to trace mechanical stress / vibration for same data about ROHS caused faults *tin whiskers from vibration, Pb-free fragility, Pb-free slow flow of cold solder.
For next iteration of stencil use guiding coaxial holes for square "nail guides".
The number of holes is 4 for board + 2 for stencil and board
The 4 board only holes are for deep nails with tops of nails and board being coplanar and can stay on path of the squeegee
The 2 additional shared holes are for board and stencil together. The CAD data for stencil must include special via pads with external diameter equal to diameter of the hole.
The placement of holes is away from solder squeegee path + approx. size of the solder paste bead
The diameter should match size of standard straight square pin of popular 0.1" header
The "anti-coining" support panels must be pinned or glued with 1-2 mm play distance from board
LOW PRIORITY
Consider adding epoxy filled variation of UTFT with custom gasket
This may be not environmentally friendly, ruggedized, high cost option for demanding applications
Board is exactly 1.6mm thick, better to reduce the board thickness if possible. To improve mechanical tolerances, reduce the board thickness to 1mm or less. Check if 4 layers boards exist for this thicknesses.
Review BOM, identify and add evidence of ROHS for every component
"LOW PRIORITY" Add column in BOM about "bright tin" vs "dull coarse tin" plating to have the awareness about "tin whisker" faults in 150 days - 5 years
This is "LOW priority issue"
ESD mitigation for users, who confuse screen to being a "touch screen".
Study the existing solutions for proper ESD protection of TFT screen
Consider adding controlled impedance path from TFT to metal panel and circuit ground (1KV 1000pF cap in parallel with 1MOhm resistor). To do so, choose most appropriate TFT pin or group of pins
Or add high value resistors (and caps if possible) from all pins to ground
Or add low value resistors in series to all pins (?) of TFT subassembly