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Software clocking details for UTFT, fuses changes for Atmel, voltage 3.4V must be documented

Software clocking details for UTFT, fuses changes for Atmel, voltage 3.4V must be documented.

  • Fuses are programmed differently to Arduino Mega R3
  • Main UTFT library has no example for 8MHz clocking - add it.
  • External clocking for SSD1963 has special requirement for wiring of unused inputs - note it.
  • Voltage 3.4V is a compromise - a highest acceptable voltage by Solomon chip and potentially lowest acceptable voltage for Atmel chip when unofficially overclocked from 8MHz to 10-12-16MHz (in future).
  • Consumed current is 150 mA with local up-converter running
  • Consumed current is 30-40 mA with local up-converter not running
  • OK symptom: Consumed current is ~120 mA with local up-converter running and when Atmel chip is not programmed.
  • FAULT symptom: Consumed current is 130-140 mA with local up-converter running and when Solomon chip is miswired.
  • FAULT symptom: Consumed power is >200mA and LM regulators are hot, when there are shorting bridges.

Add white block area to silk screen to mark the manufacturing date and serial numbers by hand

Add white block area to silk screen to mark the manufacturing date and serial numbers by hand.

  • Establish dates labels (week / year), serial numbering and online journaling for future stats about faults, components supplier batches, soldering profiles, supplementary materials, packing materials
  • Attempt to trace climatic conditions / elevation (barometric) / temperature / humidity / winter freezing cycles for potential faults caused by ROHS materials ("tin whiskers") over next 5 years
  • Attempt to trace mechanical stress / vibration for same data about ROHS caused faults *tin whiskers from vibration, Pb-free fragility, Pb-free slow flow of cold solder.

For next iteration of stencil use guiding coaxial holes for square "nail guides"

For next iteration of stencil use guiding coaxial holes for square "nail guides".

  • The number of holes is 4 for board + 2 for stencil and board
  • The 4 board only holes are for deep nails with tops of nails and board being coplanar and can stay on path of the squeegee
  • The 2 additional shared holes are for board and stencil together. The CAD data for stencil must include special via pads with external diameter equal to diameter of the hole.
  • The placement of holes is away from solder squeegee path + approx. size of the solder paste bead
  • The diameter should match size of standard straight square pin of popular 0.1" header
  • The "anti-coining" support panels must be pinned or glued with 1-2 mm play distance from board

Consider using ARM based arduino chip

LOW PRIORITY
Consider using ARM based arduino chip.

  • The ARM one has higher clocking speed
  • ARM may be more electrically noisy
  • Information to study the ARM design could or could be not more easy to find, it may turn to be more secretive than expected

ESD mitigation for users, who confuse screen to being a "touch screen"

  • This is "LOW priority issue"
    ESD mitigation for users, who confuse screen to being a "touch screen".
  • Study the existing solutions for proper ESD protection of TFT screen
  • Consider adding controlled impedance path from TFT to metal panel and circuit ground (1KV 1000pF cap in parallel with 1MOhm resistor). To do so, choose most appropriate TFT pin or group of pins
  • Or add high value resistors (and caps if possible) from all pins to ground
  • Or add low value resistors in series to all pins (?) of TFT subassembly

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