an addon to AHIR for bitfile and tb generation

Assuming all communication via RIFFA channels and RIFFA drivers. automated process for instantiating corresponding channels and AHIR to RIFFA interfaces and other VHDL alterations in accordance with the VHDL file generated by AHIR. automated process for generating hardware testbench from software testbench used.

First, generate and alter all the VHDLs then compile and generate bitstream then create and compile hardware testbench

prj generation complete. Trying hand at better organization. ahirWrapper_gen complete.